#ifndef __MACH_MESSON_REG_ADDR_H
#define __MACH_MESSON_REG_ADDR_H
//CBUS REG ADDR
#include <asm/arch/io.h>
#include <asm/arch/register.h>
#include <asm/arch/ao_reg.h>
/**
CBUS registers
generate by script based on register.h(cbus_register.h)
**/
#define P_STB_TOP_CONFIG CBUS_REG_ADDR(STB_TOP_CONFIG)
#define P_TS_TOP_CONFIG CBUS_REG_ADDR(TS_TOP_CONFIG)
#define P_TS_FILE_CONFIG CBUS_REG_ADDR(TS_FILE_CONFIG)
#define P_TS_PL_PID_INDEX CBUS_REG_ADDR(TS_PL_PID_INDEX)
#define P_TS_PL_PID_DATA CBUS_REG_ADDR(TS_PL_PID_DATA)
#define P_COMM_DESC_KEY0 CBUS_REG_ADDR(COMM_DESC_KEY0)
#define P_COMM_DESC_KEY1 CBUS_REG_ADDR(COMM_DESC_KEY1)
#define P_COMM_DESC_KEY_RW CBUS_REG_ADDR(COMM_DESC_KEY_RW)
#define P_CIPLUS_KEY0 CBUS_REG_ADDR(CIPLUS_KEY0)
#define P_CIPLUS_KEY1 CBUS_REG_ADDR(CIPLUS_KEY1)
#define P_CIPLUS_KEY2 CBUS_REG_ADDR(CIPLUS_KEY2)
#define P_CIPLUS_KEY3 CBUS_REG_ADDR(CIPLUS_KEY3)
#define P_CIPLUS_KEY_WR CBUS_REG_ADDR(CIPLUS_KEY_WR)
#define P_CIPLUS_CONFIG CBUS_REG_ADDR(CIPLUS_CONFIG)
#define P_CIPLUS_ENDIAN CBUS_REG_ADDR(CIPLUS_ENDIAN)
#define P_PREG_CTLREG0_ADDR CBUS_REG_ADDR(PREG_CTLREG0_ADDR)
#define P_PREG_PAD_GPIO6_EN_N CBUS_REG_ADDR(PREG_PAD_GPIO6_EN_N)
#define P_PREG_PAD_GPIO6_O CBUS_REG_ADDR(PREG_PAD_GPIO6_O)
#define P_PREG_PAD_GPIO6_I CBUS_REG_ADDR(PREG_PAD_GPIO6_I)
#define P_PREG_JTAG_GPIO_ADDR CBUS_REG_ADDR(PREG_JTAG_GPIO_ADDR)
#define P_PREG_PAD_GPIO0_EN_N CBUS_REG_ADDR(PREG_PAD_GPIO0_EN_N)
#define P_PREG_PAD_GPIO0_O CBUS_REG_ADDR(PREG_PAD_GPIO0_O)
#define P_PREG_PAD_GPIO0_I CBUS_REG_ADDR(PREG_PAD_GPIO0_I)
#define P_PREG_PAD_GPIO1_EN_N CBUS_REG_ADDR(PREG_PAD_GPIO1_EN_N)
#define P_PREG_PAD_GPIO1_O CBUS_REG_ADDR(PREG_PAD_GPIO1_O)
#define P_PREG_PAD_GPIO1_I CBUS_REG_ADDR(PREG_PAD_GPIO1_I)
#define P_PREG_PAD_GPIO2_EN_N CBUS_REG_ADDR(PREG_PAD_GPIO2_EN_N)
#define P_PREG_PAD_GPIO2_O CBUS_REG_ADDR(PREG_PAD_GPIO2_O)
#define P_PREG_PAD_GPIO2_I CBUS_REG_ADDR(PREG_PAD_GPIO2_I)
#define P_PREG_PAD_GPIO3_EN_N CBUS_REG_ADDR(PREG_PAD_GPIO3_EN_N)
#define P_PREG_PAD_GPIO3_O CBUS_REG_ADDR(PREG_PAD_GPIO3_O)
#define P_PREG_PAD_GPIO3_I CBUS_REG_ADDR(PREG_PAD_GPIO3_I)
#define P_PREG_PAD_GPIO4_EN_N CBUS_REG_ADDR(PREG_PAD_GPIO4_EN_N)
#define P_PREG_PAD_GPIO4_O CBUS_REG_ADDR(PREG_PAD_GPIO4_O)
#define P_PREG_PAD_GPIO4_I CBUS_REG_ADDR(PREG_PAD_GPIO4_I)
#define P_PREG_PAD_GPIO5_EN_N CBUS_REG_ADDR(PREG_PAD_GPIO5_EN_N)
#define P_PREG_PAD_GPIO5_O CBUS_REG_ADDR(PREG_PAD_GPIO5_O)
#define P_PREG_PAD_GPIO5_I CBUS_REG_ADDR(PREG_PAD_GPIO5_I)
#define P_A9_STATUS1 CBUS_REG_ADDR(A9_STATUS1)
#define P_A9_CFG0 CBUS_REG_ADDR(A9_CFG0)
#define P_A9_CFG1 CBUS_REG_ADDR(A9_CFG1)
#define P_A9_CFG2 CBUS_REG_ADDR(A9_CFG2)
#define P_A9_PERIPH_BASE CBUS_REG_ADDR(A9_PERIPH_BASE)
#define P_A9_L2_REG_BASE CBUS_REG_ADDR(A9_L2_REG_BASE)
#define P_A9_L2_STATUS CBUS_REG_ADDR(A9_L2_STATUS)
#define P_A9_POR_CFG CBUS_REG_ADDR(A9_POR_CFG)
#define P_A9_STATUS2 CBUS_REG_ADDR(A9_STATUS2)
#define P_AXI_REG_EN CBUS_REG_ADDR(AXI_REG_EN)
#define P_A9_CFG3 CBUS_REG_ADDR(A9_CFG3)
#define P_A9_CFG4 CBUS_REG_ADDR(A9_CFG4)
#define P_A9_STATUS3 CBUS_REG_ADDR(A9_STATUS3)
#define P_PERIPHS_PIN_MUX_0 CBUS_REG_ADDR(PERIPHS_PIN_MUX_0)
#define P_PERIPHS_PIN_MUX_1 CBUS_REG_ADDR(PERIPHS_PIN_MUX_1)
#define P_PERIPHS_PIN_MUX_2 CBUS_REG_ADDR(PERIPHS_PIN_MUX_2)
#define P_PERIPHS_PIN_MUX_3 CBUS_REG_ADDR(PERIPHS_PIN_MUX_3)
#define P_PERIPHS_PIN_MUX_4 CBUS_REG_ADDR(PERIPHS_PIN_MUX_4)
#define P_PERIPHS_PIN_MUX_5 CBUS_REG_ADDR(PERIPHS_PIN_MUX_5)
#define P_PERIPHS_PIN_MUX_6 CBUS_REG_ADDR(PERIPHS_PIN_MUX_6)
#define P_PERIPHS_PIN_MUX_7 CBUS_REG_ADDR(PERIPHS_PIN_MUX_7)
#define P_PERIPHS_PIN_MUX_8 CBUS_REG_ADDR(PERIPHS_PIN_MUX_8)
#define P_PERIPHS_PIN_MUX_9 CBUS_REG_ADDR(PERIPHS_PIN_MUX_9)
#define P_PERIPHS_PIN_MUX_10 CBUS_REG_ADDR(PERIPHS_PIN_MUX_10)
#define P_PERIPHS_PIN_MUX_11 CBUS_REG_ADDR(PERIPHS_PIN_MUX_11)
#define P_PERIPHS_PIN_MUX_12 CBUS_REG_ADDR(PERIPHS_PIN_MUX_12)
#define P_PAD_PULL_UP_REG6 CBUS_REG_ADDR(PAD_PULL_UP_REG6)
#define P_PAD_PULL_UP_REG0 CBUS_REG_ADDR(PAD_PULL_UP_REG0)
#define P_PAD_PULL_UP_REG1 CBUS_REG_ADDR(PAD_PULL_UP_REG1)
#define P_PAD_PULL_UP_REG2 CBUS_REG_ADDR(PAD_PULL_UP_REG2)
#define P_PAD_PULL_UP_REG3 CBUS_REG_ADDR(PAD_PULL_UP_REG3)
#define P_PAD_PULL_UP_REG4 CBUS_REG_ADDR(PAD_PULL_UP_REG4)
#define P_PAD_PULL_UP_REG5 CBUS_REG_ADDR(PAD_PULL_UP_REG5)
#define P_RAND64_ADDR0 CBUS_REG_ADDR(RAND64_ADDR0)
#define P_RAND64_ADDR1 CBUS_REG_ADDR(RAND64_ADDR1)
#define P_PREG_ETHERNET_ADDR0 CBUS_REG_ADDR(PREG_ETHERNET_ADDR0)
#define P_PREG_AM_ANALOG_ADDR CBUS_REG_ADDR(PREG_AM_ANALOG_ADDR)
#define P_PREG_MALI_BYTE_CNTL CBUS_REG_ADDR(PREG_MALI_BYTE_CNTL)
#define P_PREG_WIFI_CNTL CBUS_REG_ADDR(PREG_WIFI_CNTL)
#define P_PAD_PULL_UP_EN_REG0 CBUS_REG_ADDR(PAD_PULL_UP_EN_REG0)
#define P_PAD_PULL_UP_EN_REG1 CBUS_REG_ADDR(PAD_PULL_UP_EN_REG1)
#define P_PAD_PULL_UP_EN_REG2 CBUS_REG_ADDR(PAD_PULL_UP_EN_REG2)
#define P_PAD_PULL_UP_EN_REG3 CBUS_REG_ADDR(PAD_PULL_UP_EN_REG3)
#define P_PAD_PULL_UP_EN_REG4 CBUS_REG_ADDR(PAD_PULL_UP_EN_REG4)
#define P_PAD_PULL_UP_EN_REG5 CBUS_REG_ADDR(PAD_PULL_UP_EN_REG5)
#define P_PAD_PULL_UP_EN_REG6 CBUS_REG_ADDR(PAD_PULL_UP_EN_REG6)
#define P_PROD_TEST_REG0 CBUS_REG_ADDR(PROD_TEST_REG0)
#define P_PROD_TEST_REG1 CBUS_REG_ADDR(PROD_TEST_REG1)
#define P_METAL_REVISION CBUS_REG_ADDR(METAL_REVISION)
#define P_ADC_TOP_MISC CBUS_REG_ADDR(ADC_TOP_MISC)
#define P_DPLL_TOP_MISC CBUS_REG_ADDR(DPLL_TOP_MISC)
#define P_ANALOG_TOP_MISC CBUS_REG_ADDR(ANALOG_TOP_MISC)
#define P_AM_ANALOG_TOP_REG0 CBUS_REG_ADDR(AM_ANALOG_TOP_REG0)
#define P_AM_ANALOG_TOP_REG1 CBUS_REG_ADDR(AM_ANALOG_TOP_REG1)
#define P_PREG_STICKY_REG0 CBUS_REG_ADDR(PREG_STICKY_REG0)
#define P_PREG_STICKY_REG1 CBUS_REG_ADDR(PREG_STICKY_REG1)
#define P_PREG_WRITE_ONCE_REG CBUS_REG_ADDR(PREG_WRITE_ONCE_REG)
#define P_AM_RING_OSC_REG0 CBUS_REG_ADDR(AM_RING_OSC_REG0)
#define P_SMARTCARD_REG0 CBUS_REG_ADDR(SMARTCARD_REG0)
#define P_SMARTCARD_REG1 CBUS_REG_ADDR(SMARTCARD_REG1)
#define P_SMARTCARD_REG2 CBUS_REG_ADDR(SMARTCARD_REG2)
#define P_SMARTCARD_STATUS CBUS_REG_ADDR(SMARTCARD_STATUS)
#define P_SMARTCARD_INTR CBUS_REG_ADDR(SMARTCARD_INTR)
#define P_SMARTCARD_REG5 CBUS_REG_ADDR(SMARTCARD_REG5)
#define P_SMARTCARD_REG6 CBUS_REG_ADDR(SMARTCARD_REG6)
#define P_SMARTCARD_FIFO CBUS_REG_ADDR(SMARTCARD_FIFO)
#define P_SMARTCARD_REG8 CBUS_REG_ADDR(SMARTCARD_REG8)
#define P_IR_DEC_LDR_ACTIVE CBUS_REG_ADDR(IR_DEC_LDR_ACTIVE)
#define P_IR_DEC_LDR_IDLE CBUS_REG_ADDR(IR_DEC_LDR_IDLE)
#define P_IR_DEC_LDR_REPEAT CBUS_REG_ADDR(IR_DEC_LDR_REPEAT)
#define P_IR_DEC_BIT_0 CBUS_REG_ADDR(IR_DEC_BIT_0)
#define P_IR_DEC_REG0 CBUS_REG_ADDR(IR_DEC_REG0)
#define P_IR_DEC_FRAME CBUS_REG_ADDR(IR_DEC_FRAME)
#define P_IR_DEC_STATUS CBUS_REG_ADDR(IR_DEC_STATUS)
#define P_IR_DEC_REG1 CBUS_REG_ADDR(IR_DEC_REG1)
#define P_DEMOD_ADC_SAMPLING CBUS_REG_ADDR(DEMOD_ADC_SAMPLING)
#define P_UART0_WFIFO CBUS_REG_ADDR(UART0_WFIFO)
#define P_UART0_RFIFO CBUS_REG_ADDR(UART0_RFIFO)
#define P_UART0_CONTROL CBUS_REG_ADDR(UART0_CONTROL)
#define P_UART0_STATUS CBUS_REG_ADDR(UART0_STATUS)
#define P_UART0_MISC CBUS_REG_ADDR(UART0_MISC)
#define P_UART0_REG5 CBUS_REG_ADDR(UART0_REG5)
#define P_UART1_WFIFO CBUS_REG_ADDR(UART1_WFIFO)
#define P_UART1_RFIFO CBUS_REG_ADDR(UART1_RFIFO)
#define P_UART1_CONTROL CBUS_REG_ADDR(UART1_CONTROL)
#define P_UART1_STATUS CBUS_REG_ADDR(UART1_STATUS)
#define P_UART1_MISC CBUS_REG_ADDR(UART1_MISC)
#define P_UART1_REG5 CBUS_REG_ADDR(UART1_REG5)
#define P_I2C_M_0_CONTROL_REG CBUS_REG_ADDR(I2C_M_0_CONTROL_REG)
#define P_I2C_M_0_SLAVE_ADDR CBUS_REG_ADDR(I2C_M_0_SLAVE_ADDR)
#define P_I2C_M_0_TOKEN_LIST0 CBUS_REG_ADDR(I2C_M_0_TOKEN_LIST0)
#define P_I2C_M_0_TOKEN_LIST1 CBUS_REG_ADDR(I2C_M_0_TOKEN_LIST1)
#define P_I2C_M_0_WDATA_REG0 CBUS_REG_ADDR(I2C_M_0_WDATA_REG0)
#define P_I2C_M_0_WDATA_REG1 CBUS_REG_ADDR(I2C_M_0_WDATA_REG1)
#define P_I2C_M_0_RDATA_REG0 CBUS_REG_ADDR(I2C_M_0_RDATA_REG0)
#define P_I2C_M_0_RDATA_REG1 CBUS_REG_ADDR(I2C_M_0_RDATA_REG1)
#define P_I2C_S_CONTROL_REG CBUS_REG_ADDR(I2C_S_CONTROL_REG)
#define P_I2C_S_SEND_REG CBUS_REG_ADDR(I2C_S_SEND_REG)
#define P_I2C_S_RECV_REG CBUS_REG_ADDR(I2C_S_RECV_REG)
#define P_I2C_S_CNTL1_REG CBUS_REG_ADDR(I2C_S_CNTL1_REG)
#define P_PWM_PWM_A CBUS_REG_ADDR(PWM_PWM_A)
#define P_PWM_PWM_B CBUS_REG_ADDR(PWM_PWM_B)
#define P_PWM_MISC_REG_AB CBUS_REG_ADDR(PWM_MISC_REG_AB)
#define P_PWM_DELTA_SIGMA_AB CBUS_REG_ADDR(PWM_DELTA_SIGMA_AB)
#define P_ATAPI_IDEREG0 CBUS_REG_ADDR(ATAPI_IDEREG0)
#define P_ATAPI_IDEREG1 CBUS_REG_ADDR(ATAPI_IDEREG1)
#define P_ATAPI_IDEREG2 CBUS_REG_ADDR(ATAPI_IDEREG2)
#define P_ATAPI_CYCTIME CBUS_REG_ADDR(ATAPI_CYCTIME)
#define P_ATAPI_IDETIME CBUS_REG_ADDR(ATAPI_IDETIME)
#define P_ATAPI_PIO_TIMING CBUS_REG_ADDR(ATAPI_PIO_TIMING)
#define P_ATAPI_TABLE_ADD_REG CBUS_REG_ADDR(ATAPI_TABLE_ADD_REG)
#define P_ATAPI_IDEREG3 CBUS_REG_ADDR(ATAPI_IDEREG3)
#define P_ATAPI_UDMA_REG0 CBUS_REG_ADDR(ATAPI_UDMA_REG0)
#define P_ATAPI_UDMA_REG1 CBUS_REG_ADDR(ATAPI_UDMA_REG1)
#define P_TRANS_PWMA_REG0 CBUS_REG_ADDR(TRANS_PWMA_REG0)
#define P_TRANS_PWMA_REG1 CBUS_REG_ADDR(TRANS_PWMA_REG1)
#define P_TRANS_PWMA_MUX0 CBUS_REG_ADDR(TRANS_PWMA_MUX0)
#define P_TRANS_PWMA_MUX1 CBUS_REG_ADDR(TRANS_PWMA_MUX1)
#define P_TRANS_PWMA_MUX2 CBUS_REG_ADDR(TRANS_PWMA_MUX2)
#define P_TRANS_PWMA_MUX3 CBUS_REG_ADDR(TRANS_PWMA_MUX3)
#define P_TRANS_PWMA_MUX4 CBUS_REG_ADDR(TRANS_PWMA_MUX4)
#define P_TRANS_PWMA_MUX5 CBUS_REG_ADDR(TRANS_PWMA_MUX5)
#define P_TRANS_PWMB_REG0 CBUS_REG_ADDR(TRANS_PWMB_REG0)
#define P_TRANS_PWMB_REG1 CBUS_REG_ADDR(TRANS_PWMB_REG1)
#define P_TRANS_PWMB_MUX0 CBUS_REG_ADDR(TRANS_PWMB_MUX0)
#define P_TRANS_PWMB_MUX1 CBUS_REG_ADDR(TRANS_PWMB_MUX1)
#define P_TRANS_PWMB_MUX2 CBUS_REG_ADDR(TRANS_PWMB_MUX2)
#define P_TRANS_PWMB_MUX3 CBUS_REG_ADDR(TRANS_PWMB_MUX3)
#define P_TRANS_PWMB_MUX4 CBUS_REG_ADDR(TRANS_PWMB_MUX4)
#define P_TRANS_PWMB_MUX5 CBUS_REG_ADDR(TRANS_PWMB_MUX5)
#define P_NAND_START CBUS_REG_ADDR(NAND_START)
#define P_NAND_ADR_CMD CBUS_REG_ADDR(NAND_ADR_CMD)
#define P_NAND_ADR_STS CBUS_REG_ADDR(NAND_ADR_STS)
#define P_NAND_END CBUS_REG_ADDR(NAND_END)
#define P_PWM_PWM_C CBUS_REG_ADDR(PWM_PWM_C)
#define P_PWM_PWM_D CBUS_REG_ADDR(PWM_PWM_D)
#define P_PWM_MISC_REG_CD CBUS_REG_ADDR(PWM_MISC_REG_CD)
#define P_PWM_DELTA_SIGMA_CD CBUS_REG_ADDR(PWM_DELTA_SIGMA_CD)
#define P_ISP_LED_CTRL CBUS_REG_ADDR(ISP_LED_CTRL)
#define P_ISP_LED_TIMING1 CBUS_REG_ADDR(ISP_LED_TIMING1)
#define P_ISP_LED_TIMING2 CBUS_REG_ADDR(ISP_LED_TIMING2)
#define P_ISP_LED_TIMING3 CBUS_REG_ADDR(ISP_LED_TIMING3)
#define P_ISP_LED_TIMING4 CBUS_REG_ADDR(ISP_LED_TIMING4)
#define P_ISP_LED_TIMING5 CBUS_REG_ADDR(ISP_LED_TIMING5)
#define P_ISP_LED_TIMING6 CBUS_REG_ADDR(ISP_LED_TIMING6)
#define P_SAR_ADC_REG0 CBUS_REG_ADDR(SAR_ADC_REG0)
#define P_SAR_ADC_CHAN_LIST CBUS_REG_ADDR(SAR_ADC_CHAN_LIST)
#define P_SAR_ADC_AVG_CNTL CBUS_REG_ADDR(SAR_ADC_AVG_CNTL)
#define P_SAR_ADC_REG3 CBUS_REG_ADDR(SAR_ADC_REG3)
#define P_SAR_ADC_DELAY CBUS_REG_ADDR(SAR_ADC_DELAY)
#define P_SAR_ADC_LAST_RD CBUS_REG_ADDR(SAR_ADC_LAST_RD)
#define P_SAR_ADC_FIFO_RD CBUS_REG_ADDR(SAR_ADC_FIFO_RD)
#define P_SAR_ADC_AUX_SW CBUS_REG_ADDR(SAR_ADC_AUX_SW)
#define P_SAR_ADC_CHAN_10_SW CBUS_REG_ADDR(SAR_ADC_CHAN_10_SW)
#define P_SAR_ADC_DETECT_IDLE_SW CBUS_REG_ADDR(SAR_ADC_DETECT_IDLE_SW)
#define P_SAR_ADC_DELTA_10 CBUS_REG_ADDR(SAR_ADC_DELTA_10)
#define P_PWM_PWM_E CBUS_REG_ADDR(PWM_PWM_E)
#define P_PWM_PWM_F CBUS_REG_ADDR(PWM_PWM_F)
#define P_PWM_MISC_REG_EF CBUS_REG_ADDR(PWM_MISC_REG_EF)
#define P_PWM_DELTA_SIGMA_EF CBUS_REG_ADDR(PWM_DELTA_SIGMA_EF)
#define P_UART2_WFIFO CBUS_REG_ADDR(UART2_WFIFO)
#define P_UART2_RFIFO CBUS_REG_ADDR(UART2_RFIFO)
#define P_UART2_CONTROL CBUS_REG_ADDR(UART2_CONTROL)
#define P_UART2_STATUS CBUS_REG_ADDR(UART2_STATUS)
#define P_UART2_MISC CBUS_REG_ADDR(UART2_MISC)
#define P_UART2_REG5 CBUS_REG_ADDR(UART2_REG5)
#define P_UART3_WFIFO CBUS_REG_ADDR(UART3_WFIFO)
#define P_UART3_RFIFO CBUS_REG_ADDR(UART3_RFIFO)
#define P_UART3_CONTROL CBUS_REG_ADDR(UART3_CONTROL)
#define P_UART3_STATUS CBUS_REG_ADDR(UART3_STATUS)
#define P_UART3_MISC CBUS_REG_ADDR(UART3_MISC)
#define P_UART3_REG5 CBUS_REG_ADDR(UART3_REG5)
/*#define P_RTC_ADDR0 CBUS_REG_ADDR(RTC_ADDR0)
#define P_RTC_ADDR1 CBUS_REG_ADDR(RTC_ADDR1)
#define P_RTC_ADDR2 CBUS_REG_ADDR(RTC_ADDR2)
#define P_RTC_ADDR3 CBUS_REG_ADDR(RTC_ADDR3)
#define P_RTC_ADDR4 CBUS_REG_ADDR(RTC_ADDR4)*/
#define P_MSR_CLK_DUTY CBUS_REG_ADDR(MSR_CLK_DUTY)
#define P_MSR_CLK_REG0 CBUS_REG_ADDR(MSR_CLK_REG0)
#define P_MSR_CLK_REG1 CBUS_REG_ADDR(MSR_CLK_REG1)
#define P_MSR_CLK_REG2 CBUS_REG_ADDR(MSR_CLK_REG2)
#define P_LED_PWM_REG0 CBUS_REG_ADDR(LED_PWM_REG0)
#define P_LED_PWM_REG1 CBUS_REG_ADDR(LED_PWM_REG1)
#define P_LED_PWM_REG2 CBUS_REG_ADDR(LED_PWM_REG2)
#define P_LED_PWM_REG3 CBUS_REG_ADDR(LED_PWM_REG3)
#define P_LED_PWM_REG4 CBUS_REG_ADDR(LED_PWM_REG4)
#define P_LED_PWM_REG5 CBUS_REG_ADDR(LED_PWM_REG5)
#define P_LED_PWM_REG6 CBUS_REG_ADDR(LED_PWM_REG6)
#define P_VGHL_PWM_REG0 CBUS_REG_ADDR(VGHL_PWM_REG0)
#define P_VGHL_PWM_REG1 CBUS_REG_ADDR(VGHL_PWM_REG1)
#define P_VGHL_PWM_REG2 CBUS_REG_ADDR(VGHL_PWM_REG2)
#define P_VGHL_PWM_REG3 CBUS_REG_ADDR(VGHL_PWM_REG3)
#define P_VGHL_PWM_REG4 CBUS_REG_ADDR(VGHL_PWM_REG4)
#define P_VGHL_PWM_REG5 CBUS_REG_ADDR(VGHL_PWM_REG5)
#define P_VGHL_PWM_REG6 CBUS_REG_ADDR(VGHL_PWM_REG6)
#define P_I2C_M_1_CONTROL_REG CBUS_REG_ADDR(I2C_M_1_CONTROL_REG)
#define P_I2C_M_1_SLAVE_ADDR CBUS_REG_ADDR(I2C_M_1_SLAVE_ADDR)
#define P_I2C_M_1_TOKEN_LIST0 CBUS_REG_ADDR(I2C_M_1_TOKEN_LIST0)
#define P_I2C_M_1_TOKEN_LIST1 CBUS_REG_ADDR(I2C_M_1_TOKEN_LIST1)
#define P_I2C_M_1_WDATA_REG0 CBUS_REG_ADDR(I2C_M_1_WDATA_REG0)
#define P_I2C_M_1_WDATA_REG1 CBUS_REG_ADDR(I2C_M_1_WDATA_REG1)
#define P_I2C_M_1_RDATA_REG0 CBUS_REG_ADDR(I2C_M_1_RDATA_REG0)
#define P_I2C_M_1_RDATA_REG1 CBUS_REG_ADDR(I2C_M_1_RDATA_REG1)
#define P_I2C_M_2_CONTROL_REG CBUS_REG_ADDR(I2C_M_2_CONTROL_REG)
#define P_I2C_M_2_SLAVE_ADDR CBUS_REG_ADDR(I2C_M_2_SLAVE_ADDR)
#define P_I2C_M_2_TOKEN_LIST0 CBUS_REG_ADDR(I2C_M_2_TOKEN_LIST0)
#define P_I2C_M_2_TOKEN_LIST1 CBUS_REG_ADDR(I2C_M_2_TOKEN_LIST1)
#define P_I2C_M_2_WDATA_REG0 CBUS_REG_ADDR(I2C_M_2_WDATA_REG0)
#define P_I2C_M_2_WDATA_REG1 CBUS_REG_ADDR(I2C_M_2_WDATA_REG1)
#define P_I2C_M_2_RDATA_REG0 CBUS_REG_ADDR(I2C_M_2_RDATA_REG0)
#define P_I2C_M_2_RDATA_REG1 CBUS_REG_ADDR(I2C_M_2_RDATA_REG1)
#define P_USB_ADDR0 CBUS_REG_ADDR(USB_ADDR0)
#define P_USB_ADDR1 CBUS_REG_ADDR(USB_ADDR1)
#define P_USB_ADDR2 CBUS_REG_ADDR(USB_ADDR2)
#define P_USB_ADDR3 CBUS_REG_ADDR(USB_ADDR3)
#define P_USB_ADDR4 CBUS_REG_ADDR(USB_ADDR4)
#define P_USB_ADDR5 CBUS_REG_ADDR(USB_ADDR5)
#define P_USB_ADDR6 CBUS_REG_ADDR(USB_ADDR6)
#define P_USB_ADDR7 CBUS_REG_ADDR(USB_ADDR7)
#define P_USB_ADDR8 CBUS_REG_ADDR(USB_ADDR8)
#define P_USB_ADDR9 CBUS_REG_ADDR(USB_ADDR9)
#define P_USB_ADDR10 CBUS_REG_ADDR(USB_ADDR10)
#define P_USB_ADDR11 CBUS_REG_ADDR(USB_ADDR11)
#define P_USB_ADDR12 CBUS_REG_ADDR(USB_ADDR12)
#define P_USB_ADDR13 CBUS_REG_ADDR(USB_ADDR13)
#define P_USB_ADDR14 CBUS_REG_ADDR(USB_ADDR14)
#define P_USB_ADDR15 CBUS_REG_ADDR(USB_ADDR15)
#define P_USB_ADDR16 CBUS_REG_ADDR(USB_ADDR16)
#define P_USB_ADDR17 CBUS_REG_ADDR(USB_ADDR17)
#define P_USB_ADDR18 CBUS_REG_ADDR(USB_ADDR18)
#define P_USB_ADDR19 CBUS_REG_ADDR(USB_ADDR19)
#define P_USB_ADDR20 CBUS_REG_ADDR(USB_ADDR20)
#define P_USB_ADDR21 CBUS_REG_ADDR(USB_ADDR21)
#define P_USB_ADDR22 CBUS_REG_ADDR(USB_ADDR22)
#define P_USB_ADDR23 CBUS_REG_ADDR(USB_ADDR23)
#define P_USB_ADDR24 CBUS_REG_ADDR(USB_ADDR24)
#define P_USB_ADDR25 CBUS_REG_ADDR(USB_ADDR25)
#define P_USB_ADDR26 CBUS_REG_ADDR(USB_ADDR26)
#define P_USB_ADDR27 CBUS_REG_ADDR(USB_ADDR27)
#define P_USB_ADDR28 CBUS_REG_ADDR(USB_ADDR28)
#define P_USB_ADDR29 CBUS_REG_ADDR(USB_ADDR29)
#define P_USB_ADDR30 CBUS_REG_ADDR(USB_ADDR30)
#define P_USB_ADDR31 CBUS_REG_ADDR(USB_ADDR31)
#define P_NDMA_CNTL_REG0 CBUS_REG_ADDR(NDMA_CNTL_REG0)
#define P_NDMA_TABLE_ADD_REG CBUS_REG_ADDR(NDMA_TABLE_ADD_REG)
#define P_NDMA_TDES_KEY_LO CBUS_REG_ADDR(NDMA_TDES_KEY_LO)
#define P_NDMA_TDES_KEY_HI CBUS_REG_ADDR(NDMA_TDES_KEY_HI)
#define P_NDMA_TDES_CONTROL CBUS_REG_ADDR(NDMA_TDES_CONTROL)
#define P_NDMA_RIJNDAEL_CONTROL CBUS_REG_ADDR(NDMA_RIJNDAEL_CONTROL)
#define P_NDMA_RIJNDAEL_RK_FIFO CBUS_REG_ADDR(NDMA_RIJNDAEL_RK_FIFO)
#define P_NDMA_CRC_OUT CBUS_REG_ADDR(NDMA_CRC_OUT)
#define P_NDMA_THREAD_REG CBUS_REG_ADDR(NDMA_THREAD_REG)
#define P_NDMA_THREAD_TABLE_START0 CBUS_REG_ADDR(NDMA_THREAD_TABLE_START0)
#define P_NDMA_THREAD_TABLE_CURR0 CBUS_REG_ADDR(NDMA_THREAD_TABLE_CURR0)
#define P_NDMA_THREAD_TABLE_END0 CBUS_REG_ADDR(NDMA_THREAD_TABLE_END0)
#define P_NDMA_THREAD_TABLE_START1 CBUS_REG_ADDR(NDMA_THREAD_TABLE_START1)
#define P_NDMA_THREAD_TABLE_CURR1 CBUS_REG_ADDR(NDMA_THREAD_TABLE_CURR1)
#define P_NDMA_THREAD_TABLE_END1 CBUS_REG_ADDR(NDMA_THREAD_TABLE_END1)
#define P_NDMA_THREAD_TABLE_START2 CBUS_REG_ADDR(NDMA_THREAD_TABLE_START2)
#define P_NDMA_THREAD_TABLE_CURR2 CBUS_REG_ADDR(NDMA_THREAD_TABLE_CURR2)
#define P_NDMA_THREAD_TABLE_END2 CBUS_REG_ADDR(NDMA_THREAD_TABLE_END2)
#define P_NDMA_THREAD_TABLE_START3 CBUS_REG_ADDR(NDMA_THREAD_TABLE_START3)
#define P_NDMA_THREAD_TABLE_CURR3 CBUS_REG_ADDR(NDMA_THREAD_TABLE_CURR3)
#define P_NDMA_THREAD_TABLE_END3 CBUS_REG_ADDR(NDMA_THREAD_TABLE_END3)
#define P_NDMA_CNTL_REG1 CBUS_REG_ADDR(NDMA_CNTL_REG1)
#define P_NDMA_AES_KEY_0 CBUS_REG_ADDR(NDMA_AES_KEY_0)
#define P_NDMA_AES_KEY_1 CBUS_REG_ADDR(NDMA_AES_KEY_1)
#define P_NDMA_AES_KEY_2 CBUS_REG_ADDR(NDMA_AES_KEY_2)
#define P_NDMA_AES_KEY_3 CBUS_REG_ADDR(NDMA_AES_KEY_3)
#define P_NDMA_AES_KEY_4 CBUS_REG_ADDR(NDMA_AES_KEY_4)
#define P_NDMA_AES_KEY_5 CBUS_REG_ADDR(NDMA_AES_KEY_5)
#define P_NDMA_AES_KEY_6 CBUS_REG_ADDR(NDMA_AES_KEY_6)
#define P_NDMA_AES_KEY_7 CBUS_REG_ADDR(NDMA_AES_KEY_7)
#define P_NDMA_AES_IV_0 CBUS_REG_ADDR(NDMA_AES_IV_0)
#define P_NDMA_AES_IV_1 CBUS_REG_ADDR(NDMA_AES_IV_1)
#define P_NDMA_AES_IV_2 CBUS_REG_ADDR(NDMA_AES_IV_2)
#define P_NDMA_AES_IV_3 CBUS_REG_ADDR(NDMA_AES_IV_3)
#define P_NDMA_AES_REG0 CBUS_REG_ADDR(NDMA_AES_REG0)
#define P_STREAM_EVENT_INFO CBUS_REG_ADDR(STREAM_EVENT_INFO)
#define P_STREAM_OUTPUT_CONFIG CBUS_REG_ADDR(STREAM_OUTPUT_CONFIG)
#define P_C_D_BUS_CONTROL CBUS_REG_ADDR(C_D_BUS_CONTROL)
#define P_C_DATA CBUS_REG_ADDR(C_DATA)
#define P_STREAM_BUS_CONFIG CBUS_REG_ADDR(STREAM_BUS_CONFIG)
#define P_STREAM_DATA_IN_CONFIG CBUS_REG_ADDR(STREAM_DATA_IN_CONFIG)
#define P_STREAM_WAIT_IRQ_CONFIG CBUS_REG_ADDR(STREAM_WAIT_IRQ_CONFIG)
#define P_STREAM_EVENT_CTL CBUS_REG_ADDR(STREAM_EVENT_CTL)
#define P_CMD_ARGUMENT CBUS_REG_ADDR(CMD_ARGUMENT)
#define P_CMD_SEND CBUS_REG_ADDR(CMD_SEND)
#define P_SDIO_CONFIG CBUS_REG_ADDR(SDIO_CONFIG)
#define P_SDIO_STATUS_IRQ CBUS_REG_ADDR(SDIO_STATUS_IRQ)
#define P_SDIO_IRQ_CONFIG CBUS_REG_ADDR(SDIO_IRQ_CONFIG)
#define P_SDIO_MULT_CONFIG CBUS_REG_ADDR(SDIO_MULT_CONFIG)
#define P_SDIO_M_ADDR CBUS_REG_ADDR(SDIO_M_ADDR)
#define P_SDIO_EXTENSION CBUS_REG_ADDR(SDIO_EXTENSION)
#define P_ASYNC_FIFO_REG0 CBUS_REG_ADDR(ASYNC_FIFO_REG0)
#define P_ASYNC_FIFO_REG1 CBUS_REG_ADDR(ASYNC_FIFO_REG1)
#define P_ASYNC_FIFO_REG2 CBUS_REG_ADDR(ASYNC_FIFO_REG2)
#define P_ASYNC_FIFO_REG3 CBUS_REG_ADDR(ASYNC_FIFO_REG3)
#define P_ASYNC_FIFO2_REG0 CBUS_REG_ADDR(ASYNC_FIFO2_REG0)
#define P_ASYNC_FIFO2_REG1 CBUS_REG_ADDR(ASYNC_FIFO2_REG1)
#define P_ASYNC_FIFO2_REG2 CBUS_REG_ADDR(ASYNC_FIFO2_REG2)
#define P_ASYNC_FIFO2_REG3 CBUS_REG_ADDR(ASYNC_FIFO2_REG3)
#define P_SDIO_AHB_CBUS_CTRL CBUS_REG_ADDR(SDIO_AHB_CBUS_CTRL)
#define P_SDIO_AHB_CBUS_M_DATA CBUS_REG_ADDR(SDIO_AHB_CBUS_M_DATA)
#define P_SPI_FLASH_CMD CBUS_REG_ADDR(SPI_FLASH_CMD)
#define P_SPI_FLASH_ADDR CBUS_REG_ADDR(SPI_FLASH_ADDR)
#define P_SPI_FLASH_CTRL CBUS_REG_ADDR(SPI_FLASH_CTRL)
#define P_SPI_FLASH_CTRL1 CBUS_REG_ADDR(SPI_FLASH_CTRL1)
#define P_SPI_FLASH_STATUS CBUS_REG_ADDR(SPI_FLASH_STATUS)
#define P_SPI_FLASH_CTRL2 CBUS_REG_ADDR(SPI_FLASH_CTRL2)
#define P_SPI_FLASH_CLOCK CBUS_REG_ADDR(SPI_FLASH_CLOCK)
#define P_SPI_FLASH_USER CBUS_REG_ADDR(SPI_FLASH_USER)
#define P_SPI_FLASH_USER1 CBUS_REG_ADDR(SPI_FLASH_USER1)
#define P_SPI_FLASH_USER2 CBUS_REG_ADDR(SPI_FLASH_USER2)
#define P_SPI_FLASH_USER3 CBUS_REG_ADDR(SPI_FLASH_USER3)
#define P_SPI_FLASH_USER4 CBUS_REG_ADDR(SPI_FLASH_USER4)
#define P_SPI_FLASH_SLAVE CBUS_REG_ADDR(SPI_FLASH_SLAVE)
#define P_SPI_FLASH_SLAVE1 CBUS_REG_ADDR(SPI_FLASH_SLAVE1)
#define P_SPI_FLASH_SLAVE2 CBUS_REG_ADDR(SPI_FLASH_SLAVE2)
#define P_SPI_FLASH_SLAVE3 CBUS_REG_ADDR(SPI_FLASH_SLAVE3)
#define P_SPI_FLASH_C0 CBUS_REG_ADDR(SPI_FLASH_C0)
#define P_SPI_FLASH_C1 CBUS_REG_ADDR(SPI_FLASH_C1)
#define P_SPI_FLASH_C2 CBUS_REG_ADDR(SPI_FLASH_C2)
#define P_SPI_FLASH_C3 CBUS_REG_ADDR(SPI_FLASH_C3)
#define P_SPI_FLASH_C4 CBUS_REG_ADDR(SPI_FLASH_C4)
#define P_SPI_FLASH_C5 CBUS_REG_ADDR(SPI_FLASH_C5)
#define P_SPI_FLASH_C6 CBUS_REG_ADDR(SPI_FLASH_C6)
#define P_SPI_FLASH_C7 CBUS_REG_ADDR(SPI_FLASH_C7)
#define P_SPI_FLASH_B8 CBUS_REG_ADDR(SPI_FLASH_B8)
#define P_SPI_FLASH_B9 CBUS_REG_ADDR(SPI_FLASH_B9)
#define P_SPI_FLASH_B10 CBUS_REG_ADDR(SPI_FLASH_B10)
#define P_SPI_FLASH_B11 CBUS_REG_ADDR(SPI_FLASH_B11)
#define P_SPI_FLASH_B12 CBUS_REG_ADDR(SPI_FLASH_B12)
#define P_SPI_FLASH_B13 CBUS_REG_ADDR(SPI_FLASH_B13)
#define P_SPI_FLASH_B14 CBUS_REG_ADDR(SPI_FLASH_B14)
#define P_SPI_FLASH_B15 CBUS_REG_ADDR(SPI_FLASH_B15)
#define P_I2C_M_3_CONTROL_REG CBUS_REG_ADDR(I2C_M_3_CONTROL_REG)
#define P_I2C_M_3_SLAVE_ADDR CBUS_REG_ADDR(I2C_M_3_SLAVE_ADDR)
#define P_I2C_M_3_TOKEN_LIST0 CBUS_REG_ADDR(I2C_M_3_TOKEN_LIST0)
#define P_I2C_M_3_TOKEN_LIST1 CBUS_REG_ADDR(I2C_M_3_TOKEN_LIST1)
#define P_I2C_M_3_WDATA_REG0 CBUS_REG_ADDR(I2C_M_3_WDATA_REG0)
#define P_I2C_M_3_WDATA_REG1 CBUS_REG_ADDR(I2C_M_3_WDATA_REG1)
#define P_I2C_M_3_RDATA_REG0 CBUS_REG_ADDR(I2C_M_3_RDATA_REG0)
#define P_I2C_M_3_RDATA_REG1 CBUS_REG_ADDR(I2C_M_3_RDATA_REG1)
#define P_SPICC_RXDATA CBUS_REG_ADDR(SPICC_RXDATA)
#define P_SPICC_TXDATA CBUS_REG_ADDR(SPICC_TXDATA)
#define P_SPICC_CONREG CBUS_REG_ADDR(SPICC_CONREG)
#define P_SPICC_INTREG CBUS_REG_ADDR(SPICC_INTREG)
#define P_SPICC_DMAREG CBUS_REG_ADDR(SPICC_DMAREG)
#define P_SPICC_STATREG CBUS_REG_ADDR(SPICC_STATREG)
#define P_SPICC_PERIODREG CBUS_REG_ADDR(SPICC_PERIODREG)
#define P_SPICC_TESTREG CBUS_REG_ADDR(SPICC_TESTREG)
#define P_SPICC_DRADDR CBUS_REG_ADDR(SPICC_DRADDR)
#define P_SPICC_DWADDR CBUS_REG_ADDR(SPICC_DWADDR)
#define P_SD_REG0_ARGU CBUS_REG_ADDR(SD_REG0_ARGU)
#define P_SD_REG1_SEND CBUS_REG_ADDR(SD_REG1_SEND)
#define P_SD_REG2_CNTL CBUS_REG_ADDR(SD_REG2_CNTL)
#define P_SD_REG3_STAT CBUS_REG_ADDR(SD_REG3_STAT)
#define P_SD_REG4_CLKC CBUS_REG_ADDR(SD_REG4_CLKC)
#define P_SD_REG5_ADDR CBUS_REG_ADDR(SD_REG5_ADDR)
#define P_SD_REG6_PDMA CBUS_REG_ADDR(SD_REG6_PDMA)
#define P_SD_REG7_MISC CBUS_REG_ADDR(SD_REG7_MISC)
#define P_SD_REG8_DATA CBUS_REG_ADDR(SD_REG8_DATA)
#define P_SD_REG9_ICTL CBUS_REG_ADDR(SD_REG9_ICTL)
#define P_SD_REGA_ISTA CBUS_REG_ADDR(SD_REGA_ISTA)
#define P_SD_REGB_SRST CBUS_REG_ADDR(SD_REGB_SRST)
#define P_SD_REGC_ESTA CBUS_REG_ADDR(SD_REGC_ESTA)
#define P_SD_REGD_ENHC CBUS_REG_ADDR(SD_REGD_ENHC)
#define P_SD_REGE_CLK2 CBUS_REG_ADDR(SD_REGE_CLK2)
#define P_ISA_DEBUG_REG0 CBUS_REG_ADDR(ISA_DEBUG_REG0)
#define P_ISA_DEBUG_REG1 CBUS_REG_ADDR(ISA_DEBUG_REG1)
#define P_ISA_DEBUG_REG2 CBUS_REG_ADDR(ISA_DEBUG_REG2)
#define P_ISA_DEBUG_REG3 CBUS_REG_ADDR(ISA_DEBUG_REG3)
#define P_ISA_PLL_CLK_SIM0 CBUS_REG_ADDR(ISA_PLL_CLK_SIM0)
#define P_ISA_CNTL_REG0 CBUS_REG_ADDR(ISA_CNTL_REG0)
#define P_AO_CPU_IRQ_IN0_INTR_STAT CBUS_REG_ADDR(AO_CPU_IRQ_IN0_INTR_STAT)
#define P_AO_CPU_IRQ_IN0_INTR_STAT_CLR CBUS_REG_ADDR(AO_CPU_IRQ_IN0_INTR_STAT_CLR)
#define P_AO_CPU_IRQ_IN0_INTR_MASK CBUS_REG_ADDR(AO_CPU_IRQ_IN0_INTR_MASK)
#define P_AO_CPU_IRQ_IN0_INTR_FIRQ_SEL CBUS_REG_ADDR(AO_CPU_IRQ_IN0_INTR_FIRQ_SEL)
#define P_GPIO_INTR_EDGE_POL CBUS_REG_ADDR(GPIO_INTR_EDGE_POL)
#define P_GPIO_INTR_GPIO_SEL0 CBUS_REG_ADDR(GPIO_INTR_GPIO_SEL0)
#define P_GPIO_INTR_GPIO_SEL1 CBUS_REG_ADDR(GPIO_INTR_GPIO_SEL1)
#define P_GPIO_INTR_FILTER_SEL0 CBUS_REG_ADDR(GPIO_INTR_FILTER_SEL0)
#define P_MEDIA_CPU_INTR_STAT CBUS_REG_ADDR(MEDIA_CPU_INTR_STAT)
#define P_MEDIA_CPU_INTR_STAT_CLR CBUS_REG_ADDR(MEDIA_CPU_INTR_STAT_CLR)
#define P_MEDIA_CPU_INTR_MASK CBUS_REG_ADDR(MEDIA_CPU_INTR_MASK)
#define P_MEDIA_CPU_INTR_FIRQ_SEL CBUS_REG_ADDR(MEDIA_CPU_INTR_FIRQ_SEL)
#define P_ISA_BIST_REG0 CBUS_REG_ADDR(ISA_BIST_REG0)
#define P_ISA_BIST_REG1 CBUS_REG_ADDR(ISA_BIST_REG1)
#define P_WATCHDOG_TC CBUS_REG_ADDR(WATCHDOG_TC)
#define P_WATCHDOG_RESET CBUS_REG_ADDR(WATCHDOG_RESET)
#define P_WATCHDOG_RESET_REG CBUS_REG_ADDR(WATCHDOG_RESET_REG)
#define P_AHB_ARBITER_REG CBUS_REG_ADDR(AHB_ARBITER_REG)
#define P_AHB_ARBDEC_REG CBUS_REG_ADDR(AHB_ARBDEC_REG)
#define P_AHB_ARBITER2_REG CBUS_REG_ADDR(AHB_ARBITER2_REG)
#define P_DEVICE_MMCP_CNTL CBUS_REG_ADDR(DEVICE_MMCP_CNTL)
#define P_AUDIO_MMCP_CNTL CBUS_REG_ADDR(AUDIO_MMCP_CNTL)
#define P_ISA_TIMER_MUX CBUS_REG_ADDR(ISA_TIMER_MUX)
#define P_ISA_TIMERA CBUS_REG_ADDR(ISA_TIMERA)
#define P_ISA_TIMERB CBUS_REG_ADDR(ISA_TIMERB)
#define P_ISA_TIMERC CBUS_REG_ADDR(ISA_TIMERC)
#define P_ISA_TIMERD CBUS_REG_ADDR(ISA_TIMERD)
#define P_ISA_TIMERE CBUS_REG_ADDR(ISA_TIMERE)
#define P_FBUF_ADDR CBUS_REG_ADDR(FBUF_ADDR)
#define P_SDRAM_CTL0 CBUS_REG_ADDR(SDRAM_CTL0)
#define P_SDRAM_CTL2 CBUS_REG_ADDR(SDRAM_CTL2)
#define P_SDRAM_CTL4 CBUS_REG_ADDR(SDRAM_CTL4)
#define P_SDRAM_CTL5 CBUS_REG_ADDR(SDRAM_CTL5)
#define P_SDRAM_CTL6 CBUS_REG_ADDR(SDRAM_CTL6)
#define P_SDRAM_CTL7 CBUS_REG_ADDR(SDRAM_CTL7)
#define P_SDRAM_CTL8 CBUS_REG_ADDR(SDRAM_CTL8)
#define P_AHB_MP4_MC_CTL CBUS_REG_ADDR(AHB_MP4_MC_CTL)
#define P_MEDIA_CPU_PCR CBUS_REG_ADDR(MEDIA_CPU_PCR)
#define P_MEDIA_CPU_CTL CBUS_REG_ADDR(MEDIA_CPU_CTL)
#define P_ISA_TIMER_MUX1 CBUS_REG_ADDR(ISA_TIMER_MUX1)
#define P_ISA_TIMERF CBUS_REG_ADDR(ISA_TIMERF)
#define P_ISA_TIMERG CBUS_REG_ADDR(ISA_TIMERG)
#define P_ISA_TIMERH CBUS_REG_ADDR(ISA_TIMERH)
#define P_ISA_TIMERI CBUS_REG_ADDR(ISA_TIMERI)
#define P_ABUF_WR_CTL0 CBUS_REG_ADDR(ABUF_WR_CTL0)
#define P_ABUF_WR_CTL1 CBUS_REG_ADDR(ABUF_WR_CTL1)
#define P_ABUF_WR_CTL2 CBUS_REG_ADDR(ABUF_WR_CTL2)
#define P_ABUF_WR_CTL3 CBUS_REG_ADDR(ABUF_WR_CTL3)
#define P_ABUF_RD_CTL0 CBUS_REG_ADDR(ABUF_RD_CTL0)
#define P_ABUF_RD_CTL1 CBUS_REG_ADDR(ABUF_RD_CTL1)
#define P_ABUF_RD_CTL2 CBUS_REG_ADDR(ABUF_RD_CTL2)
#define P_ABUF_RD_CTL3 CBUS_REG_ADDR(ABUF_RD_CTL3)
#define P_ABUF_ARB_CTL0 CBUS_REG_ADDR(ABUF_ARB_CTL0)
#define P_ABUF_FIFO_CTL0 CBUS_REG_ADDR(ABUF_FIFO_CTL0)
#define P_AHB_BRIDGE_CNTL_WR CBUS_REG_ADDR(AHB_BRIDGE_CNTL_WR)
#define P_AHB_BRIDGE_REMAP0 CBUS_REG_ADDR(AHB_BRIDGE_REMAP0)
#define P_AHB_BRIDGE_REMAP1 CBUS_REG_ADDR(AHB_BRIDGE_REMAP1)
#define P_AHB_BRIDGE_REMAP2 CBUS_REG_ADDR(AHB_BRIDGE_REMAP2)
#define P_AHB_BRIDGE_REMAP3 CBUS_REG_ADDR(AHB_BRIDGE_REMAP3)
#define P_AHB_BRIDGE_CNTL_REG1 CBUS_REG_ADDR(AHB_BRIDGE_CNTL_REG1)
#define P_AHB_BRIDGE_CNTL_REG2 CBUS_REG_ADDR(AHB_BRIDGE_CNTL_REG2)
#define P_IQ_OM_WIDTH CBUS_REG_ADDR(IQ_OM_WIDTH)
#define P_DBG_ADDR_START CBUS_REG_ADDR(DBG_ADDR_START)
#define P_DBG_ADDR_END CBUS_REG_ADDR(DBG_ADDR_END)
#define P_DBG_CTRL CBUS_REG_ADDR(DBG_CTRL)
#define P_DBG_LED CBUS_REG_ADDR(DBG_LED)
#define P_DBG_SWITCH CBUS_REG_ADDR(DBG_SWITCH)
#define P_DBG_VERSION CBUS_REG_ADDR(DBG_VERSION)
#define P_VERSION_CTRL CBUS_REG_ADDR(VERSION_CTRL)
#define P_RESET0_REGISTER CBUS_REG_ADDR(RESET0_REGISTER)
#define P_RESET1_REGISTER CBUS_REG_ADDR(RESET1_REGISTER)
#define P_RESET2_REGISTER CBUS_REG_ADDR(RESET2_REGISTER)
#define P_RESET3_REGISTER CBUS_REG_ADDR(RESET3_REGISTER)
#define P_RESET4_REGISTER CBUS_REG_ADDR(RESET4_REGISTER)
#define P_RESET5_REGISTER CBUS_REG_ADDR(RESET5_REGISTER)
#define P_RESET6_REGISTER CBUS_REG_ADDR(RESET6_REGISTER)
#define P_RESET7_REGISTER CBUS_REG_ADDR(RESET7_REGISTER)
#define P_RESET0_MASK CBUS_REG_ADDR(RESET0_MASK)
#define P_RESET1_MASK CBUS_REG_ADDR(RESET1_MASK)
#define P_RESET2_MASK CBUS_REG_ADDR(RESET2_MASK)
#define P_RESET3_MASK CBUS_REG_ADDR(RESET3_MASK)
#define P_RESET4_MASK CBUS_REG_ADDR(RESET4_MASK)
#define P_RESET5_MASK CBUS_REG_ADDR(RESET5_MASK)
#define P_RESET6_MASK CBUS_REG_ADDR(RESET6_MASK)
#define P_CRT_MASK CBUS_REG_ADDR(CRT_MASK)
#define P_RESET7_MASK CBUS_REG_ADDR(RESET7_MASK)
#define P_SCR_HIU CBUS_REG_ADDR(SCR_HIU)
#define P_HPG_TIMER CBUS_REG_ADDR(HPG_TIMER)
#define P_HARM_ASB_MB0 CBUS_REG_ADDR(HARM_ASB_MB0)
#define P_HARM_ASB_MB1 CBUS_REG_ADDR(HARM_ASB_MB1)
#define P_HARM_ASB_MB2 CBUS_REG_ADDR(HARM_ASB_MB2)
#define P_HARM_ASB_MB3 CBUS_REG_ADDR(HARM_ASB_MB3)
#define P_HASB_ARM_MB0 CBUS_REG_ADDR(HASB_ARM_MB0)
#define P_HASB_ARM_MB1 CBUS_REG_ADDR(HASB_ARM_MB1)
#define P_HASB_ARM_MB2 CBUS_REG_ADDR(HASB_ARM_MB2)
#define P_HASB_ARM_MB3 CBUS_REG_ADDR(HASB_ARM_MB3)
#define P_HHI_TIMER90K CBUS_REG_ADDR(HHI_TIMER90K)
#define P_HHI_MEM_PD_REG0 CBUS_REG_ADDR(HHI_MEM_PD_REG0)
#define P_HHI_VPU_MEM_PD_REG0 CBUS_REG_ADDR(HHI_VPU_MEM_PD_REG0)
#define P_HHI_VPU_MEM_PD_REG1 CBUS_REG_ADDR(HHI_VPU_MEM_PD_REG1)
#define P_HHI_AUD_DAC_CTRL CBUS_REG_ADDR(HHI_AUD_DAC_CTRL)
#define P_HHI_VIID_CLK_DIV CBUS_REG_ADDR(HHI_VIID_CLK_DIV)
#define P_HHI_VIID_CLK_CNTL CBUS_REG_ADDR(HHI_VIID_CLK_CNTL)
#define P_HHI_VIID_DIVIDER_CNTL CBUS_REG_ADDR(HHI_VIID_DIVIDER_CNTL)
#define P_HHI_GCLK_MPEG0 CBUS_REG_ADDR(HHI_GCLK_MPEG0)
#define P_HHI_GCLK_MPEG1 CBUS_REG_ADDR(HHI_GCLK_MPEG1)
#define P_HHI_GCLK_MPEG2 CBUS_REG_ADDR(HHI_GCLK_MPEG2)
#define P_HHI_GCLK_OTHER CBUS_REG_ADDR(HHI_GCLK_OTHER)
#define P_HHI_GCLK_AO CBUS_REG_ADDR(HHI_GCLK_AO)
#define P_HHI_SYS_CPU_CLK_CNTL1 CBUS_REG_ADDR(HHI_SYS_CPU_CLK_CNTL1)
#define P_HHI_VID_CLK_DIV CBUS_REG_ADDR(HHI_VID_CLK_DIV)
#define P_HHI_MPEG_CLK_CNTL CBUS_REG_ADDR(HHI_MPEG_CLK_CNTL)
#define P_HHI_AUD_CLK_CNTL CBUS_REG_ADDR(HHI_AUD_CLK_CNTL)
#define P_HHI_VID_CLK_CNTL CBUS_REG_ADDR(HHI_VID_CLK_CNTL)
#define P_HHI_WIFI_CLK_CNTL CBUS_REG_ADDR(HHI_WIFI_CLK_CNTL)
#define P_HHI_WIFI_PLL_CNTL CBUS_REG_ADDR(HHI_WIFI_PLL_CNTL)
#define P_HHI_WIFI_PLL_CNTL2 CBUS_REG_ADDR(HHI_WIFI_PLL_CNTL2)
#define P_HHI_WIFI_PLL_CNTL3 CBUS_REG_ADDR(HHI_WIFI_PLL_CNTL3)
#define P_HHI_AUD_CLK_CNTL2 CBUS_REG_ADDR(HHI_AUD_CLK_CNTL2)
#define P_HHI_VID_DIVIDER_CNTL CBUS_REG_ADDR(HHI_VID_DIVIDER_CNTL)
#define P_HHI_SYS_CPU_CLK_CNTL CBUS_REG_ADDR(HHI_SYS_CPU_CLK_CNTL)
#define P_HHI_A9_CLK_CNTL CBUS_REG_ADDR(HHI_A9_CLK_CNTL)
#define P_HHI_MALI_CLK_CNTL CBUS_REG_ADDR(HHI_MALI_CLK_CNTL)
#define P_HHI_MIPI_PHY_CLK_CNTL CBUS_REG_ADDR(HHI_MIPI_PHY_CLK_CNTL)
#define P_HHI_VPU_CLK_CNTL CBUS_REG_ADDR(HHI_VPU_CLK_CNTL)
#define P_HHI_OTHER_PLL_CNTL CBUS_REG_ADDR(HHI_OTHER_PLL_CNTL)
#define P_HHI_OTHER_PLL_CNTL2 CBUS_REG_ADDR(HHI_OTHER_PLL_CNTL2)
#define P_HHI_OTHER_PLL_CNTL3 CBUS_REG_ADDR(HHI_OTHER_PLL_CNTL3)
#define P_HHI_HDMI_CLK_CNTL CBUS_REG_ADDR(HHI_HDMI_CLK_CNTL)
#define P_HHI_DEMOD_CLK_CNTL CBUS_REG_ADDR(HHI_DEMOD_CLK_CNTL)
#define P_HHI_SATA_CLK_CNTL CBUS_REG_ADDR(HHI_SATA_CLK_CNTL)
#define P_HHI_ETH_CLK_CNTL CBUS_REG_ADDR(HHI_ETH_CLK_CNTL)
#define P_HHI_CLK_DOUBLE_CNTL CBUS_REG_ADDR(HHI_CLK_DOUBLE_CNTL)
#define P_HHI_VDEC_CLK_CNTL CBUS_REG_ADDR(HHI_VDEC_CLK_CNTL)
#define P_HHI_VDEC2_CLK_CNTL CBUS_REG_ADDR(HHI_VDEC2_CLK_CNTL)
#define P_HHI_EDP_APB_CLK_CNTL CBUS_REG_ADDR(HHI_EDP_APB_CLK_CNTL)
#define P_HHI_HDMI_PLL_CNTL CBUS_REG_ADDR(HHI_HDMI_PLL_CNTL)
#define P_HHI_HDMI_PLL_CNTL1 CBUS_REG_ADDR(HHI_HDMI_PLL_CNTL1)
#define P_HHI_HDMI_PLL_CNTL2 CBUS_REG_ADDR(HHI_HDMI_PLL_CNTL2)
#define P_HHI_HDMI_AFC_CNTL CBUS_REG_ADDR(HHI_HDMI_AFC_CNTL)
#define P_HHI_HDMIRX_CLK_CNTL CBUS_REG_ADDR(HHI_HDMIRX_CLK_CNTL)
#define P_HHI_HDMIRX_AUD_CLK_CNTL CBUS_REG_ADDR(HHI_HDMIRX_AUD_CLK_CNTL)
#define P_HHI_VID_PLL_MOD_CNTL0 CBUS_REG_ADDR(HHI_VID_PLL_MOD_CNTL0)
#define P_HHI_VID_PLL_MOD_LOW_TCNT CBUS_REG_ADDR(HHI_VID_PLL_MOD_LOW_TCNT)
#define P_HHI_VID_PLL_MOD_HIGH_TCNT CBUS_REG_ADDR(HHI_VID_PLL_MOD_HIGH_TCNT)
#define P_HHI_VID_PLL_MOD_NOM_TCNT CBUS_REG_ADDR(HHI_VID_PLL_MOD_NOM_TCNT)
#define P_HHI_USB_CLK_CNTL CBUS_REG_ADDR(HHI_USB_CLK_CNTL)
#define P_HHI_GEN_CLK_CNTL CBUS_REG_ADDR(HHI_GEN_CLK_CNTL)
#define P_HHI_GEN_CLK_CNTL2 CBUS_REG_ADDR(HHI_GEN_CLK_CNTL2)
#define P_HHI_JTAG_CONFIG CBUS_REG_ADDR(HHI_JTAG_CONFIG)
#define P_HHI_VAFE_CLKXTALIN_CNTL CBUS_REG_ADDR(HHI_VAFE_CLKXTALIN_CNTL)
#define P_HHI_VAFE_CLKOSCIN_CNTL CBUS_REG_ADDR(HHI_VAFE_CLKOSCIN_CNTL)
#define P_HHI_VAFE_CLKIN_CNTL CBUS_REG_ADDR(HHI_VAFE_CLKIN_CNTL)
#define P_HHI_TVFE_AUTOMODE_CLK_CNTL CBUS_REG_ADDR(HHI_TVFE_AUTOMODE_CLK_CNTL)
#define P_HHI_VAFE_CLKPI_CNTL CBUS_REG_ADDR(HHI_VAFE_CLKPI_CNTL)
#define P_HHI_VDIN_MEAS_CLK_CNTL CBUS_REG_ADDR(HHI_VDIN_MEAS_CLK_CNTL)
#define P_HHI_PCM2_CLK_CNTL CBUS_REG_ADDR(HHI_PCM2_CLK_CNTL)
#define P_HHI_PCM_CLK_CNTL CBUS_REG_ADDR(HHI_PCM_CLK_CNTL)
#define P_HHI_NAND_CLK_CNTL CBUS_REG_ADDR(HHI_NAND_CLK_CNTL)
#define P_HHI_ISP_LED_CLK_CNTL CBUS_REG_ADDR(HHI_ISP_LED_CLK_CNTL)
#define P_HHI_EDP_TX_PHY_CNTL0 CBUS_REG_ADDR(HHI_EDP_TX_PHY_CNTL0)
#define P_HHI_EDP_TX_PHY_CNTL1 CBUS_REG_ADDR(HHI_EDP_TX_PHY_CNTL1)
#define P_HHI_MPLL_CNTL CBUS_REG_ADDR(HHI_MPLL_CNTL)
#define P_HHI_MPLL_CNTL2 CBUS_REG_ADDR(HHI_MPLL_CNTL2)
#define P_HHI_MPLL_CNTL3 CBUS_REG_ADDR(HHI_MPLL_CNTL3)
#define P_HHI_MPLL_CNTL4 CBUS_REG_ADDR(HHI_MPLL_CNTL4)
#define P_HHI_MPLL_CNTL5 CBUS_REG_ADDR(HHI_MPLL_CNTL5)
#define P_HHI_MPLL_CNTL6 CBUS_REG_ADDR(HHI_MPLL_CNTL6)
#define P_HHI_MPLL_CNTL7 CBUS_REG_ADDR(HHI_MPLL_CNTL7)
#define P_HHI_MPLL_CNTL8 CBUS_REG_ADDR(HHI_MPLL_CNTL8)
#define P_HHI_MPLL_CNTL9 CBUS_REG_ADDR(HHI_MPLL_CNTL9)
#define P_HHI_MPLL_CNTL10 CBUS_REG_ADDR(HHI_MPLL_CNTL10)
#define P_HHI_ADC_PLL_CNTL CBUS_REG_ADDR(HHI_ADC_PLL_CNTL)
#define P_HHI_ADC_PLL_CNTL2 CBUS_REG_ADDR(HHI_ADC_PLL_CNTL2)
#define P_HHI_ADC_PLL_CNTL3 CBUS_REG_ADDR(HHI_ADC_PLL_CNTL3)
#define P_HHI_ADC_PLL_CNTL4 CBUS_REG_ADDR(HHI_ADC_PLL_CNTL4)
#define P_HHI_AUDCLK_PLL_CNTL CBUS_REG_ADDR(HHI_AUDCLK_PLL_CNTL)
#define P_HHI_AUDCLK_PLL_CNTL2 CBUS_REG_ADDR(HHI_AUDCLK_PLL_CNTL2)
#define P_HHI_AUDCLK_PLL_CNTL3 CBUS_REG_ADDR(HHI_AUDCLK_PLL_CNTL3)
#define P_HHI_AUDCLK_PLL_CNTL4 CBUS_REG_ADDR(HHI_AUDCLK_PLL_CNTL4)
#define P_HHI_AUDCLK_PLL_CNTL5 CBUS_REG_ADDR(HHI_AUDCLK_PLL_CNTL5)
#define P_HHI_AUDCLK_PLL_CNTL6 CBUS_REG_ADDR(HHI_AUDCLK_PLL_CNTL6)
#define P_HHI_L2_DDR_CLK_CNTL CBUS_REG_ADDR(HHI_L2_DDR_CLK_CNTL)
#define P_HHI_VDAC_CNTL0 CBUS_REG_ADDR(HHI_VDAC_CNTL0)
#define P_HHI_VDAC_CNTL1 CBUS_REG_ADDR(HHI_VDAC_CNTL1)
#define P_HHI_SYS_PLL_CNTL CBUS_REG_ADDR(HHI_SYS_PLL_CNTL)
#define P_HHI_SYS_PLL_CNTL2 CBUS_REG_ADDR(HHI_SYS_PLL_CNTL2)
#define P_HHI_SYS_PLL_CNTL3 CBUS_REG_ADDR(HHI_SYS_PLL_CNTL3)
#define P_HHI_SYS_PLL_CNTL4 CBUS_REG_ADDR(HHI_SYS_PLL_CNTL4)
#define P_HHI_SYS_PLL_CNTL5 CBUS_REG_ADDR(HHI_SYS_PLL_CNTL5)
#define P_HHI_DPLL_TOP_0 CBUS_REG_ADDR(HHI_DPLL_TOP_0)
#define P_HHI_DPLL_TOP_1 CBUS_REG_ADDR(HHI_DPLL_TOP_1)
#define P_HHI_VID_PLL_CNTL CBUS_REG_ADDR(HHI_VID_PLL_CNTL)
#define P_HHI_VID_PLL_CNTL2 CBUS_REG_ADDR(HHI_VID_PLL_CNTL2)
#define P_HHI_VID_PLL_CNTL3 CBUS_REG_ADDR(HHI_VID_PLL_CNTL3)
#define P_HHI_VID_PLL_CNTL4 CBUS_REG_ADDR(HHI_VID_PLL_CNTL4)
#define P_HHI_VID_PLL_CNTL5 CBUS_REG_ADDR(HHI_VID_PLL_CNTL5)
#define P_HHI_VID_PLL_CNTL6 CBUS_REG_ADDR(HHI_VID_PLL_CNTL6)
#define P_HHI_DSI_LVDS_EDP_CNTL0 CBUS_REG_ADDR(HHI_DSI_LVDS_EDP_CNTL0)
#define P_HHI_DSI_LVDS_EDP_CNTL1 CBUS_REG_ADDR(HHI_DSI_LVDS_EDP_CNTL1)
#define P_HHI_CSI_PHY_CNTL0 CBUS_REG_ADDR(HHI_CSI_PHY_CNTL0)
#define P_HHI_CSI_PHY_CNTL1 CBUS_REG_ADDR(HHI_CSI_PHY_CNTL1)
#define P_HHI_CSI_PHY_CNTL2 CBUS_REG_ADDR(HHI_CSI_PHY_CNTL2)
#define P_HHI_CSI_PHY_CNTL3 CBUS_REG_ADDR(HHI_CSI_PHY_CNTL3)
#define P_HHI_CSI_PHY_CNTL4 CBUS_REG_ADDR(HHI_CSI_PHY_CNTL4)
#define P_HHI_DIF_CSI_PHY_CNTL0 CBUS_REG_ADDR(HHI_DIF_CSI_PHY_CNTL0)
#define P_HHI_DIF_CSI_PHY_CNTL1 CBUS_REG_ADDR(HHI_DIF_CSI_PHY_CNTL1)
#define P_HHI_DIF_CSI_PHY_CNTL2 CBUS_REG_ADDR(HHI_DIF_CSI_PHY_CNTL2)
#define P_HHI_DIF_CSI_PHY_CNTL3 CBUS_REG_ADDR(HHI_DIF_CSI_PHY_CNTL3)
#define P_HHI_DIF_CSI_PHY_CNTL4 CBUS_REG_ADDR(HHI_DIF_CSI_PHY_CNTL4)
#define P_HHI_DIF_CSI_PHY_CNTL5 CBUS_REG_ADDR(HHI_DIF_CSI_PHY_CNTL5)
#define P_HHI_LVDS_TX_PHY_CNTL0 CBUS_REG_ADDR(HHI_LVDS_TX_PHY_CNTL0)
#define P_HHI_LVDS_TX_PHY_CNTL1 CBUS_REG_ADDR(HHI_LVDS_TX_PHY_CNTL1)
#define P_HHI_VID2_PLL_CNTL CBUS_REG_ADDR(HHI_VID2_PLL_CNTL)
#define P_HHI_VID2_PLL_CNTL2 CBUS_REG_ADDR(HHI_VID2_PLL_CNTL2)
#define P_HHI_VID2_PLL_CNTL3 CBUS_REG_ADDR(HHI_VID2_PLL_CNTL3)
#define P_HHI_VID2_PLL_CNTL4 CBUS_REG_ADDR(HHI_VID2_PLL_CNTL4)
#define P_HHI_VID2_PLL_CNTL5 CBUS_REG_ADDR(HHI_VID2_PLL_CNTL5)
#define P_HHI_VID2_PLL_CNTL6 CBUS_REG_ADDR(HHI_VID2_PLL_CNTL6)
#define P_HHI_HDMI_PHY_CNTL0 CBUS_REG_ADDR(HHI_HDMI_PHY_CNTL0)
#define P_HHI_HDMI_PHY_CNTL1 CBUS_REG_ADDR(HHI_HDMI_PHY_CNTL1)
#define P_HHI_HDMI_PHY_CNTL2 CBUS_REG_ADDR(HHI_HDMI_PHY_CNTL2)
#define P_PARSER_CONTROL CBUS_REG_ADDR(PARSER_CONTROL)
#define P_PARSER_FETCH_ADDR CBUS_REG_ADDR(PARSER_FETCH_ADDR)
#define P_PARSER_FETCH_CMD CBUS_REG_ADDR(PARSER_FETCH_CMD)
#define P_PARSER_FETCH_STOP_ADDR CBUS_REG_ADDR(PARSER_FETCH_STOP_ADDR)
#define P_PARSER_FETCH_LEVEL CBUS_REG_ADDR(PARSER_FETCH_LEVEL)
#define P_PARSER_CONFIG CBUS_REG_ADDR(PARSER_CONFIG)
#define P_PFIFO_WR_PTR CBUS_REG_ADDR(PFIFO_WR_PTR)
#define P_PFIFO_RD_PTR CBUS_REG_ADDR(PFIFO_RD_PTR)
#define P_PFIFO_DATA CBUS_REG_ADDR(PFIFO_DATA)
#define P_PARSER_SEARCH_PATTERN CBUS_REG_ADDR(PARSER_SEARCH_PATTERN)
#define P_PARSER_SEARCH_MASK CBUS_REG_ADDR(PARSER_SEARCH_MASK)
#define P_PARSER_INT_ENABLE CBUS_REG_ADDR(PARSER_INT_ENABLE)
#define P_PARSER_INT_STATUS CBUS_REG_ADDR(PARSER_INT_STATUS)
#define P_PARSER_SCR_CTL CBUS_REG_ADDR(PARSER_SCR_CTL)
#define P_PARSER_SCR CBUS_REG_ADDR(PARSER_SCR)
#define P_PARSER_PARAMETER CBUS_REG_ADDR(PARSER_PARAMETER)
#define P_PARSER_INSERT_DATA CBUS_REG_ADDR(PARSER_INSERT_DATA)
#define P_VAS_STREAM_ID CBUS_REG_ADDR(VAS_STREAM_ID)
#define P_VIDEO_DTS CBUS_REG_ADDR(VIDEO_DTS)
#define P_VIDEO_PTS CBUS_REG_ADDR(VIDEO_PTS)
#define P_VIDEO_PTS_DTS_WR_PTR CBUS_REG_ADDR(VIDEO_PTS_DTS_WR_PTR)
#define P_AUDIO_PTS CBUS_REG_ADDR(AUDIO_PTS)
#define P_AUDIO_PTS_WR_PTR CBUS_REG_ADDR(AUDIO_PTS_WR_PTR)
#define P_PARSER_ES_CONTROL CBUS_REG_ADDR(PARSER_ES_CONTROL)
#define P_PFIFO_MONITOR CBUS_REG_ADDR(PFIFO_MONITOR)
#define P_PARSER_VIDEO_START_PTR CBUS_REG_ADDR(PARSER_VIDEO_START_PTR)
#define P_PARSER_VIDEO_END_PTR CBUS_REG_ADDR(PARSER_VIDEO_END_PTR)
#define P_PARSER_VIDEO_WP CBUS_REG_ADDR(PARSER_VIDEO_WP)
#define P_PARSER_VIDEO_RP CBUS_REG_ADDR(PARSER_VIDEO_RP)
#define P_PARSER_VIDEO_HOLE CBUS_REG_ADDR(PARSER_VIDEO_HOLE)
#define P_PARSER_AUDIO_START_PTR CBUS_REG_ADDR(PARSER_AUDIO_START_PTR)
#define P_PARSER_AUDIO_END_PTR CBUS_REG_ADDR(PARSER_AUDIO_END_PTR)
#define P_PARSER_AUDIO_WP CBUS_REG_ADDR(PARSER_AUDIO_WP)
#define P_PARSER_AUDIO_RP CBUS_REG_ADDR(PARSER_AUDIO_RP)
#define P_PARSER_AUDIO_HOLE CBUS_REG_ADDR(PARSER_AUDIO_HOLE)
#define P_PARSER_SUB_START_PTR CBUS_REG_ADDR(PARSER_SUB_START_PTR)
#define P_PARSER_SUB_END_PTR CBUS_REG_ADDR(PARSER_SUB_END_PTR)
#define P_PARSER_SUB_WP CBUS_REG_ADDR(PARSER_SUB_WP)
#define P_PARSER_SUB_RP CBUS_REG_ADDR(PARSER_SUB_RP)
#define P_PARSER_SUB_HOLE CBUS_REG_ADDR(PARSER_SUB_HOLE)
#define P_PARSER_FETCH_INFO CBUS_REG_ADDR(PARSER_FETCH_INFO)
#define P_PARSER_STATUS CBUS_REG_ADDR(PARSER_STATUS)
#define P_PARSER_AV_WRAP_COUNT CBUS_REG_ADDR(PARSER_AV_WRAP_COUNT)
#define P_WRRSP_PARSER CBUS_REG_ADDR(WRRSP_PARSER)
#define P_PARSER_VIDEO2_START_PTR CBUS_REG_ADDR(PARSER_VIDEO2_START_PTR)
#define P_PARSER_VIDEO2_END_PTR CBUS_REG_ADDR(PARSER_VIDEO2_END_PTR)
#define P_PARSER_VIDEO2_WP CBUS_REG_ADDR(PARSER_VIDEO2_WP)
#define P_PARSER_VIDEO2_RP CBUS_REG_ADDR(PARSER_VIDEO2_RP)
#define P_PARSER_VIDEO2_HOLE CBUS_REG_ADDR(PARSER_VIDEO2_HOLE)
#define P_PARSER_AV2_WRAP_COUNT CBUS_REG_ADDR(PARSER_AV2_WRAP_COUNT)
#define P_DVIN_FRONT_END_CTRL CBUS_REG_ADDR(DVIN_FRONT_END_CTRL)
#define P_DVIN_HS_LEAD_VS_ODD CBUS_REG_ADDR(DVIN_HS_LEAD_VS_ODD)
#define P_DVIN_ACTIVE_START_PIX CBUS_REG_ADDR(DVIN_ACTIVE_START_PIX)
#define P_DVIN_ACTIVE_START_LINE CBUS_REG_ADDR(DVIN_ACTIVE_START_LINE)
#define P_DVIN_DISPLAY_SIZE CBUS_REG_ADDR(DVIN_DISPLAY_SIZE)
#define P_DVIN_CTRL_STAT CBUS_REG_ADDR(DVIN_CTRL_STAT)
#define P_AIU_958_BPF CBUS_REG_ADDR(AIU_958_BPF)
#define P_AIU_958_BRST CBUS_REG_ADDR(AIU_958_BRST)
#define P_AIU_958_LENGTH CBUS_REG_ADDR(AIU_958_LENGTH)
#define P_AIU_958_PADDSIZE CBUS_REG_ADDR(AIU_958_PADDSIZE)
#define P_AIU_958_MISC CBUS_REG_ADDR(AIU_958_MISC)
#define P_AIU_958_FORCE_LEFT CBUS_REG_ADDR(AIU_958_FORCE_LEFT)
#define P_AIU_958_DISCARD_NUM CBUS_REG_ADDR(AIU_958_DISCARD_NUM)
#define P_AIU_958_DCU_FF_CTRL CBUS_REG_ADDR(AIU_958_DCU_FF_CTRL)
#define P_AIU_958_CHSTAT_L0 CBUS_REG_ADDR(AIU_958_CHSTAT_L0)
#define P_AIU_958_CHSTAT_L1 CBUS_REG_ADDR(AIU_958_CHSTAT_L1)
#define P_AIU_958_CTRL CBUS_REG_ADDR(AIU_958_CTRL)
#define P_AIU_958_RPT CBUS_REG_ADDR(AIU_958_RPT)
#define P_AIU_I2S_MUTE_SWAP CBUS_REG_ADDR(AIU_I2S_MUTE_SWAP)
#define P_AIU_I2S_SOURCE_DESC CBUS_REG_ADDR(AIU_I2S_SOURCE_DESC)
#define P_AIU_I2S_MED_CTRL CBUS_REG_ADDR(AIU_I2S_MED_CTRL)
#define P_AIU_I2S_MED_THRESH CBUS_REG_ADDR(AIU_I2S_MED_THRESH)
#define P_AIU_I2S_DAC_CFG CBUS_REG_ADDR(AIU_I2S_DAC_CFG)
#define P_AIU_I2S_SYNC CBUS_REG_ADDR(AIU_I2S_SYNC)
#define P_AIU_I2S_MISC CBUS_REG_ADDR(AIU_I2S_MISC)
#define P_AIU_I2S_OUT_CFG CBUS_REG_ADDR(AIU_I2S_OUT_CFG)
#define P_AIU_I2S_FF_CTRL CBUS_REG_ADDR(AIU_I2S_FF_CTRL)
#define P_AIU_RST_SOFT CBUS_REG_ADDR(AIU_RST_SOFT)
#define P_AIU_CLK_CTRL CBUS_REG_ADDR(AIU_CLK_CTRL)
#define P_AIU_MIX_ADCCFG CBUS_REG_ADDR(AIU_MIX_ADCCFG)
#define P_AIU_MIX_CTRL CBUS_REG_ADDR(AIU_MIX_CTRL)
#define P_AIU_CLK_CTRL_MORE CBUS_REG_ADDR(AIU_CLK_CTRL_MORE)
#define P_AIU_958_POP CBUS_REG_ADDR(AIU_958_POP)
#define P_AIU_MIX_GAIN CBUS_REG_ADDR(AIU_MIX_GAIN)
#define P_AIU_958_SYNWORD1 CBUS_REG_ADDR(AIU_958_SYNWORD1)
#define P_AIU_958_SYNWORD2 CBUS_REG_ADDR(AIU_958_SYNWORD2)
#define P_AIU_958_SYNWORD3 CBUS_REG_ADDR(AIU_958_SYNWORD3)
#define P_AIU_958_SYNWORD1_MASK CBUS_REG_ADDR(AIU_958_SYNWORD1_MASK)
#define P_AIU_958_SYNWORD2_MASK CBUS_REG_ADDR(AIU_958_SYNWORD2_MASK)
#define P_AIU_958_SYNWORD3_MASK CBUS_REG_ADDR(AIU_958_SYNWORD3_MASK)
#define P_AIU_958_FFRDOUT_THD CBUS_REG_ADDR(AIU_958_FFRDOUT_THD)
#define P_AIU_958_LENGTH_PER_PAUSE CBUS_REG_ADDR(AIU_958_LENGTH_PER_PAUSE)
#define P_AIU_958_PAUSE_NUM CBUS_REG_ADDR(AIU_958_PAUSE_NUM)
#define P_AIU_958_PAUSE_PAYLOAD CBUS_REG_ADDR(AIU_958_PAUSE_PAYLOAD)
#define P_AIU_958_AUTO_PAUSE CBUS_REG_ADDR(AIU_958_AUTO_PAUSE)
#define P_AIU_958_PAUSE_PD_LENGTH CBUS_REG_ADDR(AIU_958_PAUSE_PD_LENGTH)
#define P_AIU_CODEC_DAC_LRCLK_CTRL CBUS_REG_ADDR(AIU_CODEC_DAC_LRCLK_CTRL)
#define P_AIU_CODEC_ADC_LRCLK_CTRL CBUS_REG_ADDR(AIU_CODEC_ADC_LRCLK_CTRL)
#define P_AIU_HDMI_CLK_DATA_CTRL CBUS_REG_ADDR(AIU_HDMI_CLK_DATA_CTRL)
#define P_AIU_CODEC_CLK_DATA_CTRL CBUS_REG_ADDR(AIU_CODEC_CLK_DATA_CTRL)
#define P_AIU_958_CHSTAT_R0 CBUS_REG_ADDR(AIU_958_CHSTAT_R0)
#define P_AIU_958_CHSTAT_R1 CBUS_REG_ADDR(AIU_958_CHSTAT_R1)
#define P_AIU_958_VALID_CTRL CBUS_REG_ADDR(AIU_958_VALID_CTRL)
#define P_AIU_AUDIO_AMP_REG0 CBUS_REG_ADDR(AIU_AUDIO_AMP_REG0)
#define P_AIU_AUDIO_AMP_REG1 CBUS_REG_ADDR(AIU_AUDIO_AMP_REG1)
#define P_AIU_AUDIO_AMP_REG2 CBUS_REG_ADDR(AIU_AUDIO_AMP_REG2)
#define P_AIU_AUDIO_AMP_REG3 CBUS_REG_ADDR(AIU_AUDIO_AMP_REG3)
#define P_AIU_AIFIFO2_CTRL CBUS_REG_ADDR(AIU_AIFIFO2_CTRL)
#define P_AIU_AIFIFO2_STATUS CBUS_REG_ADDR(AIU_AIFIFO2_STATUS)
#define P_AIU_AIFIFO2_GBIT CBUS_REG_ADDR(AIU_AIFIFO2_GBIT)
#define P_AIU_AIFIFO2_CLB CBUS_REG_ADDR(AIU_AIFIFO2_CLB)
#define P_AIU_CRC_CTRL CBUS_REG_ADDR(AIU_CRC_CTRL)
#define P_AIU_CRC_STATUS CBUS_REG_ADDR(AIU_CRC_STATUS)
#define P_AIU_CRC_SHIFT_REG CBUS_REG_ADDR(AIU_CRC_SHIFT_REG)
#define P_AIU_CRC_IREG CBUS_REG_ADDR(AIU_CRC_IREG)
#define P_AIU_CRC_CAL_REG1 CBUS_REG_ADDR(AIU_CRC_CAL_REG1)
#define P_AIU_CRC_CAL_REG0 CBUS_REG_ADDR(AIU_CRC_CAL_REG0)
#define P_AIU_CRC_POLY_COEF1 CBUS_REG_ADDR(AIU_CRC_POLY_COEF1)
#define P_AIU_CRC_POLY_COEF0 CBUS_REG_ADDR(AIU_CRC_POLY_COEF0)
#define P_AIU_CRC_BIT_SIZE1 CBUS_REG_ADDR(AIU_CRC_BIT_SIZE1)
#define P_AIU_CRC_BIT_SIZE0 CBUS_REG_ADDR(AIU_CRC_BIT_SIZE0)
#define P_AIU_CRC_BIT_CNT1 CBUS_REG_ADDR(AIU_CRC_BIT_CNT1)
#define P_AIU_CRC_BIT_CNT0 CBUS_REG_ADDR(AIU_CRC_BIT_CNT0)
#define P_AIU_AMCLK_GATE_HI CBUS_REG_ADDR(AIU_AMCLK_GATE_HI)
#define P_AIU_AMCLK_GATE_LO CBUS_REG_ADDR(AIU_AMCLK_GATE_LO)
#define P_AIU_AMCLK_MSR CBUS_REG_ADDR(AIU_AMCLK_MSR)
#define P_AIU_AUDAC_CTRL0 CBUS_REG_ADDR(AIU_AUDAC_CTRL0)
#define P_AIU_DELTA_SIGMA0 CBUS_REG_ADDR(AIU_DELTA_SIGMA0)
#define P_AIU_DELTA_SIGMA1 CBUS_REG_ADDR(AIU_DELTA_SIGMA1)
#define P_AIU_DELTA_SIGMA2 CBUS_REG_ADDR(AIU_DELTA_SIGMA2)
#define P_AIU_DELTA_SIGMA3 CBUS_REG_ADDR(AIU_DELTA_SIGMA3)
#define P_AIU_DELTA_SIGMA4 CBUS_REG_ADDR(AIU_DELTA_SIGMA4)
#define P_AIU_DELTA_SIGMA5 CBUS_REG_ADDR(AIU_DELTA_SIGMA5)
#define P_AIU_DELTA_SIGMA6 CBUS_REG_ADDR(AIU_DELTA_SIGMA6)
#define P_AIU_DELTA_SIGMA7 CBUS_REG_ADDR(AIU_DELTA_SIGMA7)
#define P_AIU_DELTA_SIGMA_LCNTS CBUS_REG_ADDR(AIU_DELTA_SIGMA_LCNTS)
#define P_AIU_DELTA_SIGMA_RCNTS CBUS_REG_ADDR(AIU_DELTA_SIGMA_RCNTS)
#define P_AIU_MEM_I2S_START_PTR CBUS_REG_ADDR(AIU_MEM_I2S_START_PTR)
#define P_AIU_MEM_I2S_RD_PTR CBUS_REG_ADDR(AIU_MEM_I2S_RD_PTR)
#define P_AIU_MEM_I2S_END_PTR CBUS_REG_ADDR(AIU_MEM_I2S_END_PTR)
#define P_AIU_MEM_I2S_MASKS CBUS_REG_ADDR(AIU_MEM_I2S_MASKS)
#define P_AIU_MEM_I2S_CONTROL CBUS_REG_ADDR(AIU_MEM_I2S_CONTROL)
#define P_AIU_MEM_IEC958_START_PTR CBUS_REG_ADDR(AIU_MEM_IEC958_START_PTR)
#define P_AIU_MEM_IEC958_RD_PTR CBUS_REG_ADDR(AIU_MEM_IEC958_RD_PTR)
#define P_AIU_MEM_IEC958_END_PTR CBUS_REG_ADDR(AIU_MEM_IEC958_END_PTR)
#define P_AIU_MEM_IEC958_MASKS CBUS_REG_ADDR(AIU_MEM_IEC958_MASKS)
#define P_AIU_MEM_IEC958_CONTROL CBUS_REG_ADDR(AIU_MEM_IEC958_CONTROL)
#define P_AIU_MEM_AIFIFO2_START_PTR CBUS_REG_ADDR(AIU_MEM_AIFIFO2_START_PTR)
#define P_AIU_MEM_AIFIFO2_CURR_PTR CBUS_REG_ADDR(AIU_MEM_AIFIFO2_CURR_PTR)
#define P_AIU_MEM_AIFIFO2_END_PTR CBUS_REG_ADDR(AIU_MEM_AIFIFO2_END_PTR)
#define P_AIU_MEM_AIFIFO2_BYTES_AVAIL CBUS_REG_ADDR(AIU_MEM_AIFIFO2_BYTES_AVAIL)
#define P_AIU_MEM_AIFIFO2_CONTROL CBUS_REG_ADDR(AIU_MEM_AIFIFO2_CONTROL)
#define P_AIU_MEM_AIFIFO2_MAN_WP CBUS_REG_ADDR(AIU_MEM_AIFIFO2_MAN_WP)
#define P_AIU_MEM_AIFIFO2_MAN_RP CBUS_REG_ADDR(AIU_MEM_AIFIFO2_MAN_RP)
#define P_AIU_MEM_AIFIFO2_LEVEL CBUS_REG_ADDR(AIU_MEM_AIFIFO2_LEVEL)
#define P_AIU_MEM_AIFIFO2_BUF_CNTL CBUS_REG_ADDR(AIU_MEM_AIFIFO2_BUF_CNTL)
#define P_AIU_MEM_I2S_MAN_WP CBUS_REG_ADDR(AIU_MEM_I2S_MAN_WP)
#define P_AIU_MEM_I2S_MAN_RP CBUS_REG_ADDR(AIU_MEM_I2S_MAN_RP)
#define P_AIU_MEM_I2S_LEVEL CBUS_REG_ADDR(AIU_MEM_I2S_LEVEL)
#define P_AIU_MEM_I2S_BUF_CNTL CBUS_REG_ADDR(AIU_MEM_I2S_BUF_CNTL)
#define P_AIU_MEM_I2S_BUF_WRAP_COUNT CBUS_REG_ADDR(AIU_MEM_I2S_BUF_WRAP_COUNT)
#define P_AIU_MEM_I2S_MEM_CTL CBUS_REG_ADDR(AIU_MEM_I2S_MEM_CTL)
#define P_AIU_MEM_IEC958_MEM_CTL CBUS_REG_ADDR(AIU_MEM_IEC958_MEM_CTL)
#define P_AIU_MEM_IEC958_WRAP_COUNT CBUS_REG_ADDR(AIU_MEM_IEC958_WRAP_COUNT)
#define P_AIU_MEM_IEC958_IRQ_LEVEL CBUS_REG_ADDR(AIU_MEM_IEC958_IRQ_LEVEL)
#define P_AIU_MEM_IEC958_MAN_WP CBUS_REG_ADDR(AIU_MEM_IEC958_MAN_WP)
#define P_AIU_MEM_IEC958_MAN_RP CBUS_REG_ADDR(AIU_MEM_IEC958_MAN_RP)
#define P_AIU_MEM_IEC958_LEVEL CBUS_REG_ADDR(AIU_MEM_IEC958_LEVEL)
#define P_AIU_MEM_IEC958_BUF_CNTL CBUS_REG_ADDR(AIU_MEM_IEC958_BUF_CNTL)
#define P_AIU_AIFIFO_CTRL CBUS_REG_ADDR(AIU_AIFIFO_CTRL)
#define P_AIU_AIFIFO_STATUS CBUS_REG_ADDR(AIU_AIFIFO_STATUS)
#define P_AIU_AIFIFO_GBIT CBUS_REG_ADDR(AIU_AIFIFO_GBIT)
#define P_AIU_AIFIFO_CLB CBUS_REG_ADDR(AIU_AIFIFO_CLB)
#define P_AIU_MEM_AIFIFO_START_PTR CBUS_REG_ADDR(AIU_MEM_AIFIFO_START_PTR)
#define P_AIU_MEM_AIFIFO_CURR_PTR CBUS_REG_ADDR(AIU_MEM_AIFIFO_CURR_PTR)
#define P_AIU_MEM_AIFIFO_END_PTR CBUS_REG_ADDR(AIU_MEM_AIFIFO_END_PTR)
#define P_AIU_MEM_AIFIFO_BYTES_AVAIL CBUS_REG_ADDR(AIU_MEM_AIFIFO_BYTES_AVAIL)
#define P_AIU_MEM_AIFIFO_CONTROL CBUS_REG_ADDR(AIU_MEM_AIFIFO_CONTROL)
#define P_AIU_MEM_AIFIFO_MAN_WP CBUS_REG_ADDR(AIU_MEM_AIFIFO_MAN_WP)
#define P_AIU_MEM_AIFIFO_MAN_RP CBUS_REG_ADDR(AIU_MEM_AIFIFO_MAN_RP)
#define P_AIU_MEM_AIFIFO_LEVEL CBUS_REG_ADDR(AIU_MEM_AIFIFO_LEVEL)
#define P_AIU_MEM_AIFIFO_BUF_CNTL CBUS_REG_ADDR(AIU_MEM_AIFIFO_BUF_CNTL)
#define P_AIU_MEM_AIFIFO_BUF_WRAP_COUNT CBUS_REG_ADDR(AIU_MEM_AIFIFO_BUF_WRAP_COUNT)
#define P_AIU_MEM_AIFIFO2_BUF_WRAP_COUNT CBUS_REG_ADDR(AIU_MEM_AIFIFO2_BUF_WRAP_COUNT)
#define P_AIU_MEM_AIFIFO_MEM_CTL CBUS_REG_ADDR(AIU_MEM_AIFIFO_MEM_CTL)
#define P_AIFIFO_TIME_STAMP_CNTL CBUS_REG_ADDR(AIFIFO_TIME_STAMP_CNTL)
#define P_AIFIFO_TIME_STAMP_SYNC_0 CBUS_REG_ADDR(AIFIFO_TIME_STAMP_SYNC_0)
#define P_AIFIFO_TIME_STAMP_SYNC_1 CBUS_REG_ADDR(AIFIFO_TIME_STAMP_SYNC_1)
#define P_AIFIFO_TIME_STAMP_0 CBUS_REG_ADDR(AIFIFO_TIME_STAMP_0)
#define P_AIFIFO_TIME_STAMP_1 CBUS_REG_ADDR(AIFIFO_TIME_STAMP_1)
#define P_AIFIFO_TIME_STAMP_2 CBUS_REG_ADDR(AIFIFO_TIME_STAMP_2)
#define P_AIFIFO_TIME_STAMP_3 CBUS_REG_ADDR(AIFIFO_TIME_STAMP_3)
#define P_AIFIFO_TIME_STAMP_LENGTH CBUS_REG_ADDR(AIFIFO_TIME_STAMP_LENGTH)
#define P_AIFIFO2_TIME_STAMP_CNTL CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_CNTL)
#define P_AIFIFO2_TIME_STAMP_SYNC_0 CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_SYNC_0)
#define P_AIFIFO2_TIME_STAMP_SYNC_1 CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_SYNC_1)
#define P_AIFIFO2_TIME_STAMP_0 CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_0)
#define P_AIFIFO2_TIME_STAMP_1 CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_1)
#define P_AIFIFO2_TIME_STAMP_2 CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_2)
#define P_AIFIFO2_TIME_STAMP_3 CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_3)
#define P_AIFIFO2_TIME_STAMP_LENGTH CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_LENGTH)
#define P_IEC958_TIME_STAMP_CNTL CBUS_REG_ADDR(IEC958_TIME_STAMP_CNTL)
#define P_IEC958_TIME_STAMP_SYNC_0 CBUS_REG_ADDR(IEC958_TIME_STAMP_SYNC_0)
#define P_IEC958_TIME_STAMP_SYNC_1 CBUS_REG_ADDR(IEC958_TIME_STAMP_SYNC_1)
#define P_IEC958_TIME_STAMP_0 CBUS_REG_ADDR(IEC958_TIME_STAMP_0)
#define P_IEC958_TIME_STAMP_1 CBUS_REG_ADDR(IEC958_TIME_STAMP_1)
#define P_IEC958_TIME_STAMP_2 CBUS_REG_ADDR(IEC958_TIME_STAMP_2)
#define P_IEC958_TIME_STAMP_3 CBUS_REG_ADDR(IEC958_TIME_STAMP_3)
#define P_IEC958_TIME_STAMP_LENGTH CBUS_REG_ADDR(IEC958_TIME_STAMP_LENGTH)
#define P_AIU_MEM_AIFIFO2_MEM_CTL CBUS_REG_ADDR(AIU_MEM_AIFIFO2_MEM_CTL)
#define P_AIU_I2S_CBUS_DDR_CNTL CBUS_REG_ADDR(AIU_I2S_CBUS_DDR_CNTL)
#define P_AIU_I2S_CBUS_DDR_WDATA CBUS_REG_ADDR(AIU_I2S_CBUS_DDR_WDATA)
#define P_AIU_I2S_CBUS_DDR_ADDR CBUS_REG_ADDR(AIU_I2S_CBUS_DDR_ADDR)
#define P_GE2D_GEN_CTRL0 CBUS_REG_ADDR(GE2D_GEN_CTRL0)
#define P_GE2D_GEN_CTRL1 CBUS_REG_ADDR(GE2D_GEN_CTRL1)
#define P_GE2D_GEN_CTRL2 CBUS_REG_ADDR(GE2D_GEN_CTRL2)
#define P_GE2D_CMD_CTRL CBUS_REG_ADDR(GE2D_CMD_CTRL)
#define P_GE2D_STATUS0 CBUS_REG_ADDR(GE2D_STATUS0)
#define P_GE2D_STATUS1 CBUS_REG_ADDR(GE2D_STATUS1)
#define P_GE2D_SRC1_DEF_COLOR CBUS_REG_ADDR(GE2D_SRC1_DEF_COLOR)
#define P_GE2D_SRC1_CLIPX_START_END CBUS_REG_ADDR(GE2D_SRC1_CLIPX_START_END)
#define P_GE2D_SRC1_CLIPY_START_END CBUS_REG_ADDR(GE2D_SRC1_CLIPY_START_END)
#define P_GE2D_SRC1_CANVAS CBUS_REG_ADDR(GE2D_SRC1_CANVAS)
#define P_GE2D_SRC1_X_START_END CBUS_REG_ADDR(GE2D_SRC1_X_START_END)
#define P_GE2D_SRC1_Y_START_END CBUS_REG_ADDR(GE2D_SRC1_Y_START_END)
#define P_GE2D_SRC1_LUT_ADDR CBUS_REG_ADDR(GE2D_SRC1_LUT_ADDR)
#define P_GE2D_SRC1_LUT_DAT CBUS_REG_ADDR(GE2D_SRC1_LUT_DAT)
#define P_GE2D_SRC1_FMT_CTRL CBUS_REG_ADDR(GE2D_SRC1_FMT_CTRL)
#define P_GE2D_SRC2_DEF_COLOR CBUS_REG_ADDR(GE2D_SRC2_DEF_COLOR)
#define P_GE2D_SRC2_CLIPX_START_END CBUS_REG_ADDR(GE2D_SRC2_CLIPX_START_END)
#define P_GE2D_SRC2_CLIPY_START_END CBUS_REG_ADDR(GE2D_SRC2_CLIPY_START_END)
#define P_GE2D_SRC2_X_START_END CBUS_REG_ADDR(GE2D_SRC2_X_START_END)
#define P_GE2D_SRC2_Y_START_END CBUS_REG_ADDR(GE2D_SRC2_Y_START_END)
#define P_GE2D_DST_CLIPX_START_END CBUS_REG_ADDR(GE2D_DST_CLIPX_START_END)
#define P_GE2D_DST_CLIPY_START_END CBUS_REG_ADDR(GE2D_DST_CLIPY_START_END)
#define P_GE2D_DST_X_START_END CBUS_REG_ADDR(GE2D_DST_X_START_END)
#define P_GE2D_DST_Y_START_END CBUS_REG_ADDR(GE2D_DST_Y_START_END)
#define P_GE2D_SRC2_DST_CANVAS CBUS_REG_ADDR(GE2D_SRC2_DST_CANVAS)
#define P_GE2D_VSC_START_PHASE_STEP CBUS_REG_ADDR(GE2D_VSC_START_PHASE_STEP)
#define P_GE2D_VSC_PHASE_SLOPE CBUS_REG_ADDR(GE2D_VSC_PHASE_SLOPE)
#define P_GE2D_VSC_INI_CTRL CBUS_REG_ADDR(GE2D_VSC_INI_CTRL)
#define P_GE2D_HSC_START_PHASE_STEP CBUS_REG_ADDR(GE2D_HSC_START_PHASE_STEP)
#define P_GE2D_HSC_PHASE_SLOPE CBUS_REG_ADDR(GE2D_HSC_PHASE_SLOPE)
#define P_GE2D_HSC_INI_CTRL CBUS_REG_ADDR(GE2D_HSC_INI_CTRL)
#define P_GE2D_HSC_ADV_CTRL CBUS_REG_ADDR(GE2D_HSC_ADV_CTRL)
#define P_GE2D_SC_MISC_CTRL CBUS_REG_ADDR(GE2D_SC_MISC_CTRL)
#define P_GE2D_VSC_NRND_POINT CBUS_REG_ADDR(GE2D_VSC_NRND_POINT)
#define P_GE2D_VSC_NRND_PHASE CBUS_REG_ADDR(GE2D_VSC_NRND_PHASE)
#define P_GE2D_HSC_NRND_POINT CBUS_REG_ADDR(GE2D_HSC_NRND_POINT)
#define P_GE2D_HSC_NRND_PHASE CBUS_REG_ADDR(GE2D_HSC_NRND_PHASE)
#define P_GE2D_MATRIX_PRE_OFFSET CBUS_REG_ADDR(GE2D_MATRIX_PRE_OFFSET)
#define P_GE2D_MATRIX_COEF00_01 CBUS_REG_ADDR(GE2D_MATRIX_COEF00_01)
#define P_GE2D_MATRIX_COEF02_10 CBUS_REG_ADDR(GE2D_MATRIX_COEF02_10)
#define P_GE2D_MATRIX_COEF11_12 CBUS_REG_ADDR(GE2D_MATRIX_COEF11_12)
#define P_GE2D_MATRIX_COEF20_21 CBUS_REG_ADDR(GE2D_MATRIX_COEF20_21)
#define P_GE2D_MATRIX_COEF22_CTRL CBUS_REG_ADDR(GE2D_MATRIX_COEF22_CTRL)
#define P_GE2D_MATRIX_OFFSET CBUS_REG_ADDR(GE2D_MATRIX_OFFSET)
#define P_GE2D_ALU_OP_CTRL CBUS_REG_ADDR(GE2D_ALU_OP_CTRL)
#define P_GE2D_ALU_CONST_COLOR CBUS_REG_ADDR(GE2D_ALU_CONST_COLOR)
#define P_GE2D_SRC1_KEY CBUS_REG_ADDR(GE2D_SRC1_KEY)
#define P_GE2D_SRC1_KEY_MASK CBUS_REG_ADDR(GE2D_SRC1_KEY_MASK)
#define P_GE2D_SRC2_KEY CBUS_REG_ADDR(GE2D_SRC2_KEY)
#define P_GE2D_SRC2_KEY_MASK CBUS_REG_ADDR(GE2D_SRC2_KEY_MASK)
#define P_GE2D_DST_BITMASK CBUS_REG_ADDR(GE2D_DST_BITMASK)
#define P_GE2D_DP_ONOFF_CTRL CBUS_REG_ADDR(GE2D_DP_ONOFF_CTRL)
#define P_GE2D_SCALE_COEF_IDX CBUS_REG_ADDR(GE2D_SCALE_COEF_IDX)
#define P_GE2D_SCALE_COEF CBUS_REG_ADDR(GE2D_SCALE_COEF)
#define P_GE2D_SRC_OUTSIDE_ALPHA CBUS_REG_ADDR(GE2D_SRC_OUTSIDE_ALPHA)
#define P_GE2D_ANTIFLICK_CTRL0 CBUS_REG_ADDR(GE2D_ANTIFLICK_CTRL0)
#define P_GE2D_ANTIFLICK_CTRL1 CBUS_REG_ADDR(GE2D_ANTIFLICK_CTRL1)
#define P_GE2D_ANTIFLICK_COLOR_FILT0 CBUS_REG_ADDR(GE2D_ANTIFLICK_COLOR_FILT0)
#define P_GE2D_ANTIFLICK_COLOR_FILT1 CBUS_REG_ADDR(GE2D_ANTIFLICK_COLOR_FILT1)
#define P_GE2D_ANTIFLICK_COLOR_FILT2 CBUS_REG_ADDR(GE2D_ANTIFLICK_COLOR_FILT2)
#define P_GE2D_ANTIFLICK_COLOR_FILT3 CBUS_REG_ADDR(GE2D_ANTIFLICK_COLOR_FILT3)
#define P_GE2D_ANTIFLICK_ALPHA_FILT0 CBUS_REG_ADDR(GE2D_ANTIFLICK_ALPHA_FILT0)
#define P_GE2D_ANTIFLICK_ALPHA_FILT1 CBUS_REG_ADDR(GE2D_ANTIFLICK_ALPHA_FILT1)
#define P_GE2D_ANTIFLICK_ALPHA_FILT2 CBUS_REG_ADDR(GE2D_ANTIFLICK_ALPHA_FILT2)
#define P_GE2D_ANTIFLICK_ALPHA_FILT3 CBUS_REG_ADDR(GE2D_ANTIFLICK_ALPHA_FILT3)
#define P_GE2D_SRC1_RANGE_MAP_Y_CTRL CBUS_REG_ADDR(GE2D_SRC1_RANGE_MAP_Y_CTRL)
#define P_GE2D_SRC1_RANGE_MAP_CB_CTRL CBUS_REG_ADDR(GE2D_SRC1_RANGE_MAP_CB_CTRL)
#define P_GE2D_SRC1_RANGE_MAP_CR_CTRL CBUS_REG_ADDR(GE2D_SRC1_RANGE_MAP_CR_CTRL)
#define P_GE2D_ARB_BURST_NUM CBUS_REG_ADDR(GE2D_ARB_BURST_NUM)
#define P_GE2D_TID_TOKEN CBUS_REG_ADDR(GE2D_TID_TOKEN)
#define P_GE2D_GEN_CTRL3 CBUS_REG_ADDR(GE2D_GEN_CTRL3)
#define P_GE2D_STATUS2 CBUS_REG_ADDR(GE2D_STATUS2)
#define P_GE2D_GEN_CTRL4 CBUS_REG_ADDR(GE2D_GEN_CTRL4)
#define P_AUDIO_COP_CTL2 CBUS_REG_ADDR(AUDIO_COP_CTL2)
#define P_OPERAND_M_CTL CBUS_REG_ADDR(OPERAND_M_CTL)
#define P_OPERAND1_ADDR CBUS_REG_ADDR(OPERAND1_ADDR)
#define P_OPERAND2_ADDR CBUS_REG_ADDR(OPERAND2_ADDR)
#define P_RESULT_M_CTL CBUS_REG_ADDR(RESULT_M_CTL)
#define P_RESULT1_ADDR CBUS_REG_ADDR(RESULT1_ADDR)
#define P_RESULT2_ADDR CBUS_REG_ADDR(RESULT2_ADDR)
#define P_ADD_SHFT_CTL CBUS_REG_ADDR(ADD_SHFT_CTL)
#define P_OPERAND_ONE_H CBUS_REG_ADDR(OPERAND_ONE_H)
#define P_OPERAND_ONE_L CBUS_REG_ADDR(OPERAND_ONE_L)
#define P_OPERAND_TWO_H CBUS_REG_ADDR(OPERAND_TWO_H)
#define P_OPERAND_TWO_L CBUS_REG_ADDR(OPERAND_TWO_L)
#define P_RESULT_H CBUS_REG_ADDR(RESULT_H)
#define P_RESULT_M CBUS_REG_ADDR(RESULT_M)
#define P_RESULT_L CBUS_REG_ADDR(RESULT_L)
#define P_WMEM_R_PTR CBUS_REG_ADDR(WMEM_R_PTR)
#define P_WMEM_W_PTR CBUS_REG_ADDR(WMEM_W_PTR)
#define P_AUDIO_LAYER CBUS_REG_ADDR(AUDIO_LAYER)
#define P_AC3_DECODING CBUS_REG_ADDR(AC3_DECODING)
#define P_AC3_DYNAMIC CBUS_REG_ADDR(AC3_DYNAMIC)
#define P_AC3_MELODY CBUS_REG_ADDR(AC3_MELODY)
#define P_AC3_VOCAL CBUS_REG_ADDR(AC3_VOCAL)
#define P_ASSIST_AMR_SCRATCH0 CBUS_REG_ADDR(ASSIST_AMR_SCRATCH0)
#define P_ASSIST_AMR_SCRATCH1 CBUS_REG_ADDR(ASSIST_AMR_SCRATCH1)
#define P_ASSIST_AMR_SCRATCH2 CBUS_REG_ADDR(ASSIST_AMR_SCRATCH2)
#define P_ASSIST_AMR_SCRATCH3 CBUS_REG_ADDR(ASSIST_AMR_SCRATCH3)
#define P_ASSIST_HW_REV CBUS_REG_ADDR(ASSIST_HW_REV)
#define P_ASSIST_POR_CONFIG CBUS_REG_ADDR(ASSIST_POR_CONFIG)
#define P_ASSIST_SPARE16_REG1 CBUS_REG_ADDR(ASSIST_SPARE16_REG1)
#define P_ASSIST_SPARE16_REG2 CBUS_REG_ADDR(ASSIST_SPARE16_REG2)
#define P_ASSIST_SPARE8_REG1 CBUS_REG_ADDR(ASSIST_SPARE8_REG1)
#define P_ASSIST_SPARE8_REG2 CBUS_REG_ADDR(ASSIST_SPARE8_REG2)
#define P_ASSIST_SPARE8_REG3 CBUS_REG_ADDR(ASSIST_SPARE8_REG3)
#define P_AC3_CTRL_REG1 CBUS_REG_ADDR(AC3_CTRL_REG1)
#define P_AC3_CTRL_REG2 CBUS_REG_ADDR(AC3_CTRL_REG2)
#define P_AC3_CTRL_REG3 CBUS_REG_ADDR(AC3_CTRL_REG3)
#define P_AC3_CTRL_REG4 CBUS_REG_ADDR(AC3_CTRL_REG4)
#define P_ASSIST_GEN_CNTL CBUS_REG_ADDR(ASSIST_GEN_CNTL)
#define P_EE_ASSIST_MBOX0_IRQ_REG CBUS_REG_ADDR(EE_ASSIST_MBOX0_IRQ_REG)
#define P_EE_ASSIST_MBOX0_CLR_REG CBUS_REG_ADDR(EE_ASSIST_MBOX0_CLR_REG)
#define P_EE_ASSIST_MBOX0_MASK CBUS_REG_ADDR(EE_ASSIST_MBOX0_MASK)
#define P_EE_ASSIST_MBOX0_FIQ_SEL CBUS_REG_ADDR(EE_ASSIST_MBOX0_FIQ_SEL)
#define P_EE_ASSIST_MBOX1_IRQ_REG CBUS_REG_ADDR(EE_ASSIST_MBOX1_IRQ_REG)
#define P_EE_ASSIST_MBOX1_CLR_REG CBUS_REG_ADDR(EE_ASSIST_MBOX1_CLR_REG)
#define P_EE_ASSIST_MBOX1_MASK CBUS_REG_ADDR(EE_ASSIST_MBOX1_MASK)
#define P_EE_ASSIST_MBOX1_FIQ_SEL CBUS_REG_ADDR(EE_ASSIST_MBOX1_FIQ_SEL)
#define P_EE_ASSIST_MBOX2_IRQ_REG CBUS_REG_ADDR(EE_ASSIST_MBOX2_IRQ_REG)
#define P_EE_ASSIST_MBOX2_CLR_REG CBUS_REG_ADDR(EE_ASSIST_MBOX2_CLR_REG)
#define P_EE_ASSIST_MBOX2_MASK CBUS_REG_ADDR(EE_ASSIST_MBOX2_MASK)
#define P_EE_ASSIST_MBOX2_FIQ_SEL CBUS_REG_ADDR(EE_ASSIST_MBOX2_FIQ_SEL)
#define P_EE_ASSIST_MBOX3_IRQ_REG CBUS_REG_ADDR(EE_ASSIST_MBOX3_IRQ_REG)
#define P_EE_ASSIST_MBOX3_CLR_REG CBUS_REG_ADDR(EE_ASSIST_MBOX3_CLR_REG)
#define P_EE_ASSIST_MBOX3_MASK CBUS_REG_ADDR(EE_ASSIST_MBOX3_MASK)
#define P_EE_ASSIST_MBOX3_FIQ_SEL CBUS_REG_ADDR(EE_ASSIST_MBOX3_FIQ_SEL)
#define P_AUDIN_SPDIF_MODE CBUS_REG_ADDR(AUDIN_SPDIF_MODE)
#define P_AUDIN_SPDIF_FS_CLK_RLTN CBUS_REG_ADDR(AUDIN_SPDIF_FS_CLK_RLTN)
#define P_AUDIN_SPDIF_CHNL_STS_A CBUS_REG_ADDR(AUDIN_SPDIF_CHNL_STS_A)
#define P_AUDIN_SPDIF_CHNL_STS_B CBUS_REG_ADDR(AUDIN_SPDIF_CHNL_STS_B)
#define P_AUDIN_SPDIF_MISC CBUS_REG_ADDR(AUDIN_SPDIF_MISC)
#define P_AUDIN_SPDIF_NPCM_PCPD CBUS_REG_ADDR(AUDIN_SPDIF_NPCM_PCPD)
#define P_AUDIN_SPDIF_END CBUS_REG_ADDR(AUDIN_SPDIF_END)
#define P_AUDIN_I2SIN_CTRL CBUS_REG_ADDR(AUDIN_I2SIN_CTRL)
#define P_AUDIN_SOURCE_SEL CBUS_REG_ADDR(AUDIN_SOURCE_SEL)
#define P_AUDIN_DECODE_FORMAT CBUS_REG_ADDR(AUDIN_DECODE_FORMAT)
#define P_AUDIN_DECODE_CONTROL_STATUS CBUS_REG_ADDR(AUDIN_DECODE_CONTROL_STATUS)
#define P_AUDIN_DECODE_CHANNEL_STATUS_A_0 CBUS_REG_ADDR(AUDIN_DECODE_CHANNEL_STATUS_A_0)
#define P_AUDIN_DECODE_CHANNEL_STATUS_A_1 CBUS_REG_ADDR(AUDIN_DECODE_CHANNEL_STATUS_A_1)
#define P_AUDIN_DECODE_CHANNEL_STATUS_A_2 CBUS_REG_ADDR(AUDIN_DECODE_CHANNEL_STATUS_A_2)
#define P_AUDIN_DECODE_CHANNEL_STATUS_A_3 CBUS_REG_ADDR(AUDIN_DECODE_CHANNEL_STATUS_A_3)
#define P_AUDIN_DECODE_CHANNEL_STATUS_A_4 CBUS_REG_ADDR(AUDIN_DECODE_CHANNEL_STATUS_A_4)
#define P_AUDIN_DECODE_CHANNEL_STATUS_A_5 CBUS_REG_ADDR(AUDIN_DECODE_CHANNEL_STATUS_A_5)
#define P_AUDIN_FIFO0_START CBUS_REG_ADDR(AUDIN_FIFO0_START)
#define P_AUDIN_FIFO0_END CBUS_REG_ADDR(AUDIN_FIFO0_END)
#define P_AUDIN_FIFO0_PTR CBUS_REG_ADDR(AUDIN_FIFO0_PTR)
#define P_AUDIN_FIFO0_INTR CBUS_REG_ADDR(AUDIN_FIFO0_INTR)
#define P_AUDIN_FIFO0_RDPTR CBUS_REG_ADDR(AUDIN_FIFO0_RDPTR)
#define P_AUDIN_FIFO0_CTRL CBUS_REG_ADDR(AUDIN_FIFO0_CTRL)
#define P_AUDIN_FIFO0_CTRL1 CBUS_REG_ADDR(AUDIN_FIFO0_CTRL1)
#define P_AUDIN_FIFO0_LVL0 CBUS_REG_ADDR(AUDIN_FIFO0_LVL0)
#define P_AUDIN_FIFO0_LVL1 CBUS_REG_ADDR(AUDIN_FIFO0_LVL1)
#define P_AUDIN_FIFO0_LVL2 CBUS_REG_ADDR(AUDIN_FIFO0_LVL2)
#define P_AUDIN_FIFO0_REQID CBUS_REG_ADDR(AUDIN_FIFO0_REQID)
#define P_AUDIN_FIFO0_WRAP CBUS_REG_ADDR(AUDIN_FIFO0_WRAP)
#define P_AUDIN_FIFO1_START CBUS_REG_ADDR(AUDIN_FIFO1_START)
#define P_AUDIN_FIFO1_END CBUS_REG_ADDR(AUDIN_FIFO1_END)
#define P_AUDIN_FIFO1_PTR CBUS_REG_ADDR(AUDIN_FIFO1_PTR)
#define P_AUDIN_FIFO1_INTR CBUS_REG_ADDR(AUDIN_FIFO1_INTR)
#define P_AUDIN_FIFO1_RDPTR CBUS_REG_ADDR(AUDIN_FIFO1_RDPTR)
#define P_AUDIN_FIFO1_CTRL CBUS_REG_ADDR(AUDIN_FIFO1_CTRL)
#define P_AUDIN_FIFO1_CTRL1 CBUS_REG_ADDR(AUDIN_FIFO1_CTRL1)
#define P_AUDIN_FIFO1_LVL0 CBUS_REG_ADDR(AUDIN_FIFO1_LVL0)
#define P_AUDIN_FIFO1_LVL1 CBUS_REG_ADDR(AUDIN_FIFO1_LVL1)
#define P_AUDIN_FIFO1_LVL2 CBUS_REG_ADDR(AUDIN_FIFO1_LVL2)
#define P_AUDIN_FIFO1_REQID CBUS_REG_ADDR(AUDIN_FIFO1_REQID)
#define P_AUDIN_FIFO1_WRAP CBUS_REG_ADDR(AUDIN_FIFO1_WRAP)
#define P_AUDIN_FIFO2_START CBUS_REG_ADDR(AUDIN_FIFO2_START)
#define P_AUDIN_FIFO2_END CBUS_REG_ADDR(AUDIN_FIFO2_END)
#define P_AUDIN_FIFO2_PTR CBUS_REG_ADDR(AUDIN_FIFO2_PTR)
#define P_AUDIN_FIFO2_INTR CBUS_REG_ADDR(AUDIN_FIFO2_INTR)
#define P_AUDIN_FIFO2_RDPTR CBUS_REG_ADDR(AUDIN_FIFO2_RDPTR)
#define P_AUDIN_FIFO2_CTRL CBUS_REG_ADDR(AUDIN_FIFO2_CTRL)
#define P_AUDIN_FIFO2_CTRL1 CBUS_REG_ADDR(AUDIN_FIFO2_CTRL1)
#define P_AUDIN_FIFO2_LVL0 CBUS_REG_ADDR(AUDIN_FIFO2_LVL0)
#define P_AUDIN_FIFO2_LVL1 CBUS_REG_ADDR(AUDIN_FIFO2_LVL1)
#define P_AUDIN_FIFO2_LVL2 CBUS_REG_ADDR(AUDIN_FIFO2_LVL2)
#define P_AUDIN_FIFO2_REQID CBUS_REG_ADDR(AUDIN_FIFO2_REQID)
#define P_AUDIN_FIFO2_WRAP CBUS_REG_ADDR(AUDIN_FIFO2_WRAP)
#define P_AUDIN_INT_CTRL CBUS_REG_ADDR(AUDIN_INT_CTRL)
#define P_AUDIN_FIFO_INT CBUS_REG_ADDR(AUDIN_FIFO_INT)
#define P_PCMIN_CTRL0 CBUS_REG_ADDR(PCMIN_CTRL0)
#define P_PCMIN_CTRL1 CBUS_REG_ADDR(PCMIN_CTRL1)
#define P_PCMIN1_CTRL0 CBUS_REG_ADDR(PCMIN1_CTRL0)
#define P_PCMIN1_CTRL1 CBUS_REG_ADDR(PCMIN1_CTRL1)
#define P_PCMOUT_CTRL0 CBUS_REG_ADDR(PCMOUT_CTRL0)
#define P_PCMOUT_CTRL1 CBUS_REG_ADDR(PCMOUT_CTRL1)
#define P_PCMOUT_CTRL2 CBUS_REG_ADDR(PCMOUT_CTRL2)
#define P_PCMOUT_CTRL3 CBUS_REG_ADDR(PCMOUT_CTRL3)
#define P_PCMOUT1_CTRL0 CBUS_REG_ADDR(PCMOUT1_CTRL0)
#define P_PCMOUT1_CTRL1 CBUS_REG_ADDR(PCMOUT1_CTRL1)
#define P_PCMOUT1_CTRL2 CBUS_REG_ADDR(PCMOUT1_CTRL2)
#define P_PCMOUT1_CTRL3 CBUS_REG_ADDR(PCMOUT1_CTRL3)
#define P_AUDOUT_CTRL CBUS_REG_ADDR(AUDOUT_CTRL)
#define P_AUDOUT_CTRL1 CBUS_REG_ADDR(AUDOUT_CTRL1)
#define P_AUDOUT_BUF0_STA CBUS_REG_ADDR(AUDOUT_BUF0_STA)
#define P_AUDOUT_BUF0_EDA CBUS_REG_ADDR(AUDOUT_BUF0_EDA)
#define P_AUDOUT_BUF0_WPTR CBUS_REG_ADDR(AUDOUT_BUF0_WPTR)
#define P_AUDOUT_BUF1_STA CBUS_REG_ADDR(AUDOUT_BUF1_STA)
#define P_AUDOUT_BUF1_EDA CBUS_REG_ADDR(AUDOUT_BUF1_EDA)
#define P_AUDOUT_BUF1_WPTR CBUS_REG_ADDR(AUDOUT_BUF1_WPTR)
#define P_AUDOUT_FIFO_RPTR CBUS_REG_ADDR(AUDOUT_FIFO_RPTR)
#define P_AUDOUT_INTR_PTR CBUS_REG_ADDR(AUDOUT_INTR_PTR)
#define P_AUDOUT_FIFO_STS CBUS_REG_ADDR(AUDOUT_FIFO_STS)
#define P_AUDOUT1_CTRL CBUS_REG_ADDR(AUDOUT1_CTRL)
#define P_AUDOUT1_CTRL1 CBUS_REG_ADDR(AUDOUT1_CTRL1)
#define P_AUDOUT1_BUF0_STA CBUS_REG_ADDR(AUDOUT1_BUF0_STA)
#define P_AUDOUT1_BUF0_EDA CBUS_REG_ADDR(AUDOUT1_BUF0_EDA)
#define P_AUDOUT1_BUF0_WPTR CBUS_REG_ADDR(AUDOUT1_BUF0_WPTR)
#define P_AUDOUT1_BUF1_STA CBUS_REG_ADDR(AUDOUT1_BUF1_STA)
#define P_AUDOUT1_BUF1_EDA CBUS_REG_ADDR(AUDOUT1_BUF1_EDA)
#define P_AUDOUT1_BUF1_WPTR CBUS_REG_ADDR(AUDOUT1_BUF1_WPTR)
#define P_AUDOUT1_FIFO_RPTR CBUS_REG_ADDR(AUDOUT1_FIFO_RPTR)
#define P_AUDOUT1_INTR_PTR CBUS_REG_ADDR(AUDOUT1_INTR_PTR)
#define P_AUDOUT1_FIFO_STS CBUS_REG_ADDR(AUDOUT1_FIFO_STS)
#define P_AUDIN_HDMI_MEAS_CTRL CBUS_REG_ADDR(AUDIN_HDMI_MEAS_CTRL)
#define P_AUDIN_HDMI_MEAS_CYCLES_M1 CBUS_REG_ADDR(AUDIN_HDMI_MEAS_CYCLES_M1)
#define P_AUDIN_HDMI_MEAS_INTR_MASKN CBUS_REG_ADDR(AUDIN_HDMI_MEAS_INTR_MASKN)
#define P_AUDIN_HDMI_MEAS_INTR_STAT CBUS_REG_ADDR(AUDIN_HDMI_MEAS_INTR_STAT)
#define P_AUDIN_HDMI_REF_CYCLES_STAT_0 CBUS_REG_ADDR(AUDIN_HDMI_REF_CYCLES_STAT_0)
#define P_AUDIN_HDMI_REF_CYCLES_STAT_1 CBUS_REG_ADDR(AUDIN_HDMI_REF_CYCLES_STAT_1)
#define P_AUDIN_HDMIRX_AFIFO_STAT CBUS_REG_ADDR(AUDIN_HDMIRX_AFIFO_STAT)
#define P_AUDIN_FIFO0_PIO_STS CBUS_REG_ADDR(AUDIN_FIFO0_PIO_STS)
#define P_AUDIN_FIFO0_PIO_RDL CBUS_REG_ADDR(AUDIN_FIFO0_PIO_RDL)
#define P_AUDIN_FIFO0_PIO_RDH CBUS_REG_ADDR(AUDIN_FIFO0_PIO_RDH)
#define P_AUDIN_FIFO1_PIO_STS CBUS_REG_ADDR(AUDIN_FIFO1_PIO_STS)
#define P_AUDIN_FIFO1_PIO_RDL CBUS_REG_ADDR(AUDIN_FIFO1_PIO_RDL)
#define P_AUDIN_FIFO1_PIO_RDH CBUS_REG_ADDR(AUDIN_FIFO1_PIO_RDH)
#define P_AUDIN_FIFO2_PIO_STS CBUS_REG_ADDR(AUDIN_FIFO2_PIO_STS)
#define P_AUDIN_FIFO2_PIO_RDL CBUS_REG_ADDR(AUDIN_FIFO2_PIO_RDL)
#define P_AUDIN_FIFO2_PIO_RDH CBUS_REG_ADDR(AUDIN_FIFO2_PIO_RDH)
#define P_AUDOUT_FIFO_PIO_STS CBUS_REG_ADDR(AUDOUT_FIFO_PIO_STS)
#define P_AUDOUT_FIFO_PIO_WRL CBUS_REG_ADDR(AUDOUT_FIFO_PIO_WRL)
#define P_AUDOUT_FIFO_PIO_WRH CBUS_REG_ADDR(AUDOUT_FIFO_PIO_WRH)
#define P_AUDOUT1_FIFO_PIO_STS CBUS_REG_ADDR(AUDOUT1_FIFO_PIO_STS)
#define P_AUDOUT1_FIFO_PIO_WRL CBUS_REG_ADDR(AUDOUT1_FIFO_PIO_WRL)
#define P_AUDOUT1_FIFO_PIO_WRH CBUS_REG_ADDR(AUDOUT1_FIFO_PIO_WRH)
#define P_AUDIN_ADDR_END CBUS_REG_ADDR(AUDIN_ADDR_END)
#define P_VDIN0_OFFSET CBUS_REG_ADDR(VDIN0_OFFSET)
#define P_VDIN1_OFFSET CBUS_REG_ADDR(VDIN1_OFFSET)
#define P_VDIN_SCALE_COEF_IDX CBUS_REG_ADDR(VDIN_SCALE_COEF_IDX)
#define P_VDIN_SCALE_COEF CBUS_REG_ADDR(VDIN_SCALE_COEF)
#define P_VDIN_COM_CTRL0 CBUS_REG_ADDR(VDIN_COM_CTRL0)
#define P_VDIN_ACTIVE_MAX_PIX_CNT_STATUS CBUS_REG_ADDR(VDIN_ACTIVE_MAX_PIX_CNT_STATUS)
#define P_VDIN_LCNT_STATUS CBUS_REG_ADDR(VDIN_LCNT_STATUS)
#define P_VDIN_COM_STATUS0 CBUS_REG_ADDR(VDIN_COM_STATUS0)
#define P_VDIN_COM_STATUS1 CBUS_REG_ADDR(VDIN_COM_STATUS1)
#define P_VDIN_LCNT_SHADOW_STATUS CBUS_REG_ADDR(VDIN_LCNT_SHADOW_STATUS)
#define P_VDIN_ASFIFO_CTRL0 CBUS_REG_ADDR(VDIN_ASFIFO_CTRL0)
#define P_VDIN_ASFIFO_CTRL1 CBUS_REG_ADDR(VDIN_ASFIFO_CTRL1)
#define P_VDIN_WIDTHM1I_WIDTHM1O CBUS_REG_ADDR(VDIN_WIDTHM1I_WIDTHM1O)
#define P_VDIN_SC_MISC_CTRL CBUS_REG_ADDR(VDIN_SC_MISC_CTRL)
#define P_VDIN_HSC_PHASE_STEP CBUS_REG_ADDR(VDIN_HSC_PHASE_STEP)
#define P_VDIN_HSC_INI_CTRL CBUS_REG_ADDR(VDIN_HSC_INI_CTRL)
#define P_VDIN_COM_STATUS2 CBUS_REG_ADDR(VDIN_COM_STATUS2)
#define P_VDIN_ASFIFO_CTRL2 CBUS_REG_ADDR(VDIN_ASFIFO_CTRL2)
#define P_VDIN_MATRIX_CTRL CBUS_REG_ADDR(VDIN_MATRIX_CTRL)
#define P_VDIN_MATRIX_COEF00_01 CBUS_REG_ADDR(VDIN_MATRIX_COEF00_01)
#define P_VDIN_MATRIX_COEF02_10 CBUS_REG_ADDR(VDIN_MATRIX_COEF02_10)
#define P_VDIN_MATRIX_COEF11_12 CBUS_REG_ADDR(VDIN_MATRIX_COEF11_12)
#define P_VDIN_MATRIX_COEF20_21 CBUS_REG_ADDR(VDIN_MATRIX_COEF20_21)
#define P_VDIN_MATRIX_COEF22 CBUS_REG_ADDR(VDIN_MATRIX_COEF22)
#define P_VDIN_MATRIX_OFFSET0_1 CBUS_REG_ADDR(VDIN_MATRIX_OFFSET0_1)
#define P_VDIN_MATRIX_OFFSET2 CBUS_REG_ADDR(VDIN_MATRIX_OFFSET2)
#define P_VDIN_MATRIX_PRE_OFFSET0_1 CBUS_REG_ADDR(VDIN_MATRIX_PRE_OFFSET0_1)
#define P_VDIN_MATRIX_PRE_OFFSET2 CBUS_REG_ADDR(VDIN_MATRIX_PRE_OFFSET2)
#define P_VDIN_LFIFO_CTRL CBUS_REG_ADDR(VDIN_LFIFO_CTRL)
#define P_VDIN_COM_GCLK_CTRL CBUS_REG_ADDR(VDIN_COM_GCLK_CTRL)
#define P_VDIN_INTF_WIDTHM1 CBUS_REG_ADDR(VDIN_INTF_WIDTHM1)
#define P_VDIN_WR_CTRL2 CBUS_REG_ADDR(VDIN_WR_CTRL2)
#define P_VDIN_WR_CTRL CBUS_REG_ADDR(VDIN_WR_CTRL)
#define P_VDIN_WR_H_START_END CBUS_REG_ADDR(VDIN_WR_H_START_END)
#define P_VDIN_WR_V_START_END CBUS_REG_ADDR(VDIN_WR_V_START_END)
#define P_VDIN_VSC_PHASE_STEP CBUS_REG_ADDR(VDIN_VSC_PHASE_STEP)
#define P_VDIN_VSC_INI_CTRL CBUS_REG_ADDR(VDIN_VSC_INI_CTRL)
#define P_VDIN_SCIN_HEIGHTM1 CBUS_REG_ADDR(VDIN_SCIN_HEIGHTM1)
#define P_VDIN_DUMMY_DATA CBUS_REG_ADDR(VDIN_DUMMY_DATA)
#define P_VDIN_MATRIX_PROBE_COLOR CBUS_REG_ADDR(VDIN_MATRIX_PROBE_COLOR)
#define P_VDIN_MATRIX_HL_COLOR CBUS_REG_ADDR(VDIN_MATRIX_HL_COLOR)
#define P_VDIN_MATRIX_PROBE_POS CBUS_REG_ADDR(VDIN_MATRIX_PROBE_POS)
#define P_VDIN_CHROMA_ADDR_PORT CBUS_REG_ADDR(VDIN_CHROMA_ADDR_PORT)
#define P_VDIN_CHROMA_DATA_PORT CBUS_REG_ADDR(VDIN_CHROMA_DATA_PORT)
#define P_VDIN_CM_BRI_CON_CTRL CBUS_REG_ADDR(VDIN_CM_BRI_CON_CTRL)
#define P_VDIN_GO_LINE_CTRL CBUS_REG_ADDR(VDIN_GO_LINE_CTRL)
#define P_VDIN_HIST_CTRL CBUS_REG_ADDR(VDIN_HIST_CTRL)
#define P_VDIN_HIST_H_START_END CBUS_REG_ADDR(VDIN_HIST_H_START_END)
#define P_VDIN_HIST_V_START_END CBUS_REG_ADDR(VDIN_HIST_V_START_END)
#define P_VDIN_HIST_MAX_MIN CBUS_REG_ADDR(VDIN_HIST_MAX_MIN)
#define P_VDIN_HIST_SPL_VAL CBUS_REG_ADDR(VDIN_HIST_SPL_VAL)
#define P_VDIN_HIST_SPL_PIX_CNT CBUS_REG_ADDR(VDIN_HIST_SPL_PIX_CNT)
#define P_VDIN_HIST_CHROMA_SUM CBUS_REG_ADDR(VDIN_HIST_CHROMA_SUM)
#define P_VDIN_DNLP_HIST00 CBUS_REG_ADDR(VDIN_DNLP_HIST00)
#define P_VDIN_DNLP_HIST01 CBUS_REG_ADDR(VDIN_DNLP_HIST01)
#define P_VDIN_DNLP_HIST02 CBUS_REG_ADDR(VDIN_DNLP_HIST02)
#define P_VDIN_DNLP_HIST03 CBUS_REG_ADDR(VDIN_DNLP_HIST03)
#define P_VDIN_DNLP_HIST04 CBUS_REG_ADDR(VDIN_DNLP_HIST04)
#define P_VDIN_DNLP_HIST05 CBUS_REG_ADDR(VDIN_DNLP_HIST05)
#define P_VDIN_DNLP_HIST06 CBUS_REG_ADDR(VDIN_DNLP_HIST06)
#define P_VDIN_DNLP_HIST07 CBUS_REG_ADDR(VDIN_DNLP_HIST07)
#define P_VDIN_DNLP_HIST08 CBUS_REG_ADDR(VDIN_DNLP_HIST08)
#define P_VDIN_DNLP_HIST09 CBUS_REG_ADDR(VDIN_DNLP_HIST09)
#define P_VDIN_DNLP_HIST10 CBUS_REG_ADDR(VDIN_DNLP_HIST10)
#define P_VDIN_DNLP_HIST11 CBUS_REG_ADDR(VDIN_DNLP_HIST11)
#define P_VDIN_DNLP_HIST12 CBUS_REG_ADDR(VDIN_DNLP_HIST12)
#define P_VDIN_DNLP_HIST13 CBUS_REG_ADDR(VDIN_DNLP_HIST13)
#define P_VDIN_DNLP_HIST14 CBUS_REG_ADDR(VDIN_DNLP_HIST14)
#define P_VDIN_DNLP_HIST15 CBUS_REG_ADDR(VDIN_DNLP_HIST15)
#define P_VDIN_DNLP_HIST16 CBUS_REG_ADDR(VDIN_DNLP_HIST16)
#define P_VDIN_DNLP_HIST17 CBUS_REG_ADDR(VDIN_DNLP_HIST17)
#define P_VDIN_DNLP_HIST18 CBUS_REG_ADDR(VDIN_DNLP_HIST18)
#define P_VDIN_DNLP_HIST19 CBUS_REG_ADDR(VDIN_DNLP_HIST19)
#define P_VDIN_DNLP_HIST20 CBUS_REG_ADDR(VDIN_DNLP_HIST20)
#define P_VDIN_DNLP_HIST21 CBUS_REG_ADDR(VDIN_DNLP_HIST21)
#define P_VDIN_DNLP_HIST22 CBUS_REG_ADDR(VDIN_DNLP_HIST22)
#define P_VDIN_DNLP_HIST23 CBUS_REG_ADDR(VDIN_DNLP_HIST23)
#define P_VDIN_DNLP_HIST24 CBUS_REG_ADDR(VDIN_DNLP_HIST24)
#define P_VDIN_DNLP_HIST25 CBUS_REG_ADDR(VDIN_DNLP_HIST25)
#define P_VDIN_DNLP_HIST26 CBUS_REG_ADDR(VDIN_DNLP_HIST26)
#define P_VDIN_DNLP_HIST27 CBUS_REG_ADDR(VDIN_DNLP_HIST27)
#define P_VDIN_DNLP_HIST28 CBUS_REG_ADDR(VDIN_DNLP_HIST28)
#define P_VDIN_DNLP_HIST29 CBUS_REG_ADDR(VDIN_DNLP_HIST29)
#define P_VDIN_DNLP_HIST30 CBUS_REG_ADDR(VDIN_DNLP_HIST30)
#define P_VDIN_DNLP_HIST31 CBUS_REG_ADDR(VDIN_DNLP_HIST31)
#define P_VDIN_LDIM_STTS_HIST_REGION_IDX CBUS_REG_ADDR(VDIN_LDIM_STTS_HIST_REGION_IDX)
#define P_VDIN_LDIM_STTS_HIST_SET_REGION CBUS_REG_ADDR(VDIN_LDIM_STTS_HIST_SET_REGION)
#define P_VDIN_LDIM_STTS_HIST_READ_REGION CBUS_REG_ADDR(VDIN_LDIM_STTS_HIST_READ_REGION)
#define P_VDIN_MEAS_CTRL0 CBUS_REG_ADDR(VDIN_MEAS_CTRL0)
#define P_VDIN_MEAS_VS_COUNT_HI CBUS_REG_ADDR(VDIN_MEAS_VS_COUNT_HI)
#define P_VDIN_MEAS_VS_COUNT_LO CBUS_REG_ADDR(VDIN_MEAS_VS_COUNT_LO)
#define P_VDIN_MEAS_HS_RANGE CBUS_REG_ADDR(VDIN_MEAS_HS_RANGE)
#define P_VDIN_MEAS_HS_COUNT CBUS_REG_ADDR(VDIN_MEAS_HS_COUNT)
#define P_VDIN_BLKBAR_CTRL1 CBUS_REG_ADDR(VDIN_BLKBAR_CTRL1)
#define P_VDIN_BLKBAR_CTRL0 CBUS_REG_ADDR(VDIN_BLKBAR_CTRL0)
#define P_VDIN_BLKBAR_H_START_END CBUS_REG_ADDR(VDIN_BLKBAR_H_START_END)
#define P_VDIN_BLKBAR_V_START_END CBUS_REG_ADDR(VDIN_BLKBAR_V_START_END)
#define P_VDIN_BLKBAR_CNT_THRESHOLD CBUS_REG_ADDR(VDIN_BLKBAR_CNT_THRESHOLD)
#define P_VDIN_BLKBAR_ROW_TH1_TH2 CBUS_REG_ADDR(VDIN_BLKBAR_ROW_TH1_TH2)
#define P_VDIN_BLKBAR_IND_LEFT_START_END CBUS_REG_ADDR(VDIN_BLKBAR_IND_LEFT_START_END)
#define P_VDIN_BLKBAR_IND_RIGHT_START_END CBUS_REG_ADDR(VDIN_BLKBAR_IND_RIGHT_START_END)
#define P_VDIN_BLKBAR_IND_LEFT1_CNT CBUS_REG_ADDR(VDIN_BLKBAR_IND_LEFT1_CNT)
#define P_VDIN_BLKBAR_IND_LEFT2_CNT CBUS_REG_ADDR(VDIN_BLKBAR_IND_LEFT2_CNT)
#define P_VDIN_BLKBAR_IND_RIGHT1_CNT CBUS_REG_ADDR(VDIN_BLKBAR_IND_RIGHT1_CNT)
#define P_VDIN_BLKBAR_IND_RIGHT2_CNT CBUS_REG_ADDR(VDIN_BLKBAR_IND_RIGHT2_CNT)
#define P_VDIN_BLKBAR_STATUS0 CBUS_REG_ADDR(VDIN_BLKBAR_STATUS0)
#define P_VDIN_BLKBAR_STATUS1 CBUS_REG_ADDR(VDIN_BLKBAR_STATUS1)
#define P_VDIN_WIN_H_START_END CBUS_REG_ADDR(VDIN_WIN_H_START_END)
#define P_VDIN_WIN_V_START_END CBUS_REG_ADDR(VDIN_WIN_V_START_END)
#define P_VDIN_ASFIFO_CTRL3 CBUS_REG_ADDR(VDIN_ASFIFO_CTRL3)
#define P_VDIN0_SCALE_COEF_IDX CBUS_REG_ADDR(VDIN0_SCALE_COEF_IDX)
#define P_VDIN0_SCALE_COEF CBUS_REG_ADDR(VDIN0_SCALE_COEF)
#define P_VDIN0_COM_CTRL0 CBUS_REG_ADDR(VDIN0_COM_CTRL0)
#define P_VDIN0_ACTIVE_MAX_PIX_CNT_STATUS CBUS_REG_ADDR(VDIN0_ACTIVE_MAX_PIX_CNT_STATUS)
#define P_VDIN0_LCNT_STATUS CBUS_REG_ADDR(VDIN0_LCNT_STATUS)
#define P_VDIN0_COM_STATUS0 CBUS_REG_ADDR(VDIN0_COM_STATUS0)
#define P_VDIN0_COM_STATUS1 CBUS_REG_ADDR(VDIN0_COM_STATUS1)
#define P_VDIN0_LCNT_SHADOW_STATUS CBUS_REG_ADDR(VDIN0_LCNT_SHADOW_STATUS)
#define P_VDIN0_ASFIFO_CTRL0 CBUS_REG_ADDR(VDIN0_ASFIFO_CTRL0)
#define P_VDIN0_ASFIFO_CTRL1 CBUS_REG_ADDR(VDIN0_ASFIFO_CTRL1)
#define P_VDIN0_WIDTHM1I_WIDTHM1O CBUS_REG_ADDR(VDIN0_WIDTHM1I_WIDTHM1O)
#define P_VDIN0_SC_MISC_CTRL CBUS_REG_ADDR(VDIN0_SC_MISC_CTRL)
#define P_VDIN0_HSC_PHASE_STEP CBUS_REG_ADDR(VDIN0_HSC_PHASE_STEP)
#define P_VDIN0_HSC_INI_CTRL CBUS_REG_ADDR(VDIN0_HSC_INI_CTRL)
#define P_VDIN0_COM_STATUS2 CBUS_REG_ADDR(VDIN0_COM_STATUS2)
#define P_VDIN0_ASFIFO_CTRL2 CBUS_REG_ADDR(VDIN0_ASFIFO_CTRL2)
#define P_VDIN0_MATRIX_CTRL CBUS_REG_ADDR(VDIN0_MATRIX_CTRL)
#define P_VDIN0_MATRIX_COEF00_01 CBUS_REG_ADDR(VDIN0_MATRIX_COEF00_01)
#define P_VDIN0_MATRIX_COEF02_10 CBUS_REG_ADDR(VDIN0_MATRIX_COEF02_10)
#define P_VDIN0_MATRIX_COEF11_12 CBUS_REG_ADDR(VDIN0_MATRIX_COEF11_12)
#define P_VDIN0_MATRIX_COEF20_21 CBUS_REG_ADDR(VDIN0_MATRIX_COEF20_21)
#define P_VDIN0_MATRIX_COEF22 CBUS_REG_ADDR(VDIN0_MATRIX_COEF22)
#define P_VDIN0_MATRIX_OFFSET0_1 CBUS_REG_ADDR(VDIN0_MATRIX_OFFSET0_1)
#define P_VDIN0_MATRIX_OFFSET2 CBUS_REG_ADDR(VDIN0_MATRIX_OFFSET2)
#define P_VDIN0_MATRIX_PRE_OFFSET0_1 CBUS_REG_ADDR(VDIN0_MATRIX_PRE_OFFSET0_1)
#define P_VDIN0_MATRIX_PRE_OFFSET2 CBUS_REG_ADDR(VDIN0_MATRIX_PRE_OFFSET2)
#define P_VDIN0_LFIFO_CTRL CBUS_REG_ADDR(VDIN0_LFIFO_CTRL)
#define P_VDIN0_COM_GCLK_CTRL CBUS_REG_ADDR(VDIN0_COM_GCLK_CTRL)
#define P_VDIN0_INTF_WIDTHM1 CBUS_REG_ADDR(VDIN0_INTF_WIDTHM1)
#define P_VDIN0_WR_CTRL2 CBUS_REG_ADDR(VDIN0_WR_CTRL2)
#define P_VDIN0_WR_CTRL CBUS_REG_ADDR(VDIN0_WR_CTRL)
#define P_VDIN0_WR_H_START_END CBUS_REG_ADDR(VDIN0_WR_H_START_END)
#define P_VDIN0_WR_V_START_END CBUS_REG_ADDR(VDIN0_WR_V_START_END)
#define P_VDIN0_VSC_PHASE_STEP CBUS_REG_ADDR(VDIN0_VSC_PHASE_STEP)
#define P_VDIN0_VSC_INI_CTRL CBUS_REG_ADDR(VDIN0_VSC_INI_CTRL)
#define P_VDIN0_SCIN_HEIGHTM1 CBUS_REG_ADDR(VDIN0_SCIN_HEIGHTM1)
#define P_VDIN0_DUMMY_DATA CBUS_REG_ADDR(VDIN0_DUMMY_DATA)
#define P_VDIN0_MATRIX_PROBE_COLOR CBUS_REG_ADDR(VDIN0_MATRIX_PROBE_COLOR)
#define P_VDIN0_MATRIX_HL_COLOR CBUS_REG_ADDR(VDIN0_MATRIX_HL_COLOR)
#define P_VDIN0_MATRIX_PROBE_POS CBUS_REG_ADDR(VDIN0_MATRIX_PROBE_POS)
#define P_VDIN0_CHROMA_ADDR_PORT CBUS_REG_ADDR(VDIN0_CHROMA_ADDR_PORT)
#define P_VDIN0_CHROMA_DATA_PORT CBUS_REG_ADDR(VDIN0_CHROMA_DATA_PORT)
#define P_VDIN0_CM_BRI_CON_CTRL CBUS_REG_ADDR(VDIN0_CM_BRI_CON_CTRL)
#define P_VDIN0_HIST_CTRL CBUS_REG_ADDR(VDIN0_HIST_CTRL)
#define P_VDIN0_HIST_H_START_END CBUS_REG_ADDR(VDIN0_HIST_H_START_END)
#define P_VDIN0_HIST_V_START_END CBUS_REG_ADDR(VDIN0_HIST_V_START_END)
#define P_VDIN0_HIST_MAX_MIN CBUS_REG_ADDR(VDIN0_HIST_MAX_MIN)
#define P_VDIN0_HIST_SPL_VAL CBUS_REG_ADDR(VDIN0_HIST_SPL_VAL)
#define P_VDIN0_HIST_SPL_PIX_CNT CBUS_REG_ADDR(VDIN0_HIST_SPL_PIX_CNT)
#define P_VDIN0_HIST_CHROMA_SUM CBUS_REG_ADDR(VDIN0_HIST_CHROMA_SUM)
#define P_VDIN0_DNLP_HIST00 CBUS_REG_ADDR(VDIN0_DNLP_HIST00)
#define P_VDIN0_DNLP_HIST01 CBUS_REG_ADDR(VDIN0_DNLP_HIST01)
#define P_VDIN0_DNLP_HIST02 CBUS_REG_ADDR(VDIN0_DNLP_HIST02)
#define P_VDIN0_DNLP_HIST03 CBUS_REG_ADDR(VDIN0_DNLP_HIST03)
#define P_VDIN0_DNLP_HIST04 CBUS_REG_ADDR(VDIN0_DNLP_HIST04)
#define P_VDIN0_DNLP_HIST05 CBUS_REG_ADDR(VDIN0_DNLP_HIST05)
#define P_VDIN0_DNLP_HIST06 CBUS_REG_ADDR(VDIN0_DNLP_HIST06)
#define P_VDIN0_DNLP_HIST07 CBUS_REG_ADDR(VDIN0_DNLP_HIST07)
#define P_VDIN0_DNLP_HIST08 CBUS_REG_ADDR(VDIN0_DNLP_HIST08)
#define P_VDIN0_DNLP_HIST09 CBUS_REG_ADDR(VDIN0_DNLP_HIST09)
#define P_VDIN0_DNLP_HIST10 CBUS_REG_ADDR(VDIN0_DNLP_HIST10)
#define P_VDIN0_DNLP_HIST11 CBUS_REG_ADDR(VDIN0_DNLP_HIST11)
#define P_VDIN0_DNLP_HIST12 CBUS_REG_ADDR(VDIN0_DNLP_HIST12)
#define P_VDIN0_DNLP_HIST13 CBUS_REG_ADDR(VDIN0_DNLP_HIST13)
#define P_VDIN0_DNLP_HIST14 CBUS_REG_ADDR(VDIN0_DNLP_HIST14)
#define P_VDIN0_DNLP_HIST15 CBUS_REG_ADDR(VDIN0_DNLP_HIST15)
#define P_VDIN0_DNLP_HIST16 CBUS_REG_ADDR(VDIN0_DNLP_HIST16)
#define P_VDIN0_DNLP_HIST17 CBUS_REG_ADDR(VDIN0_DNLP_HIST17)
#define P_VDIN0_DNLP_HIST18 CBUS_REG_ADDR(VDIN0_DNLP_HIST18)
#define P_VDIN0_DNLP_HIST19 CBUS_REG_ADDR(VDIN0_DNLP_HIST19)
#define P_VDIN0_DNLP_HIST20 CBUS_REG_ADDR(VDIN0_DNLP_HIST20)
#define P_VDIN0_DNLP_HIST21 CBUS_REG_ADDR(VDIN0_DNLP_HIST21)
#define P_VDIN0_DNLP_HIST22 CBUS_REG_ADDR(VDIN0_DNLP_HIST22)
#define P_VDIN0_DNLP_HIST23 CBUS_REG_ADDR(VDIN0_DNLP_HIST23)
#define P_VDIN0_DNLP_HIST24 CBUS_REG_ADDR(VDIN0_DNLP_HIST24)
#define P_VDIN0_DNLP_HIST25 CBUS_REG_ADDR(VDIN0_DNLP_HIST25)
#define P_VDIN0_DNLP_HIST26 CBUS_REG_ADDR(VDIN0_DNLP_HIST26)
#define P_VDIN0_DNLP_HIST27 CBUS_REG_ADDR(VDIN0_DNLP_HIST27)
#define P_VDIN0_DNLP_HIST28 CBUS_REG_ADDR(VDIN0_DNLP_HIST28)
#define P_VDIN0_DNLP_HIST29 CBUS_REG_ADDR(VDIN0_DNLP_HIST29)
#define P_VDIN0_DNLP_HIST30 CBUS_REG_ADDR(VDIN0_DNLP_HIST30)
#define P_VDIN0_DNLP_HIST31 CBUS_REG_ADDR(VDIN0_DNLP_HIST31)
#define P_VDIN0_LDIM_STTS_HIST_REGION_IDX CBUS_REG_ADDR(VDIN0_LDIM_STTS_HIST_REGION_IDX)
#define P_VDIN0_LDIM_STTS_HIST_SET_REGION CBUS_REG_ADDR(VDIN0_LDIM_STTS_HIST_SET_REGION)
#define P_VDIN0_LDIM_STTS_HIST_READ_REGION CBUS_REG_ADDR(VDIN0_LDIM_STTS_HIST_READ_REGION)
#define P_VDIN0_MEAS_CTRL0 CBUS_REG_ADDR(VDIN0_MEAS_CTRL0)
#define P_VDIN0_MEAS_VS_COUNT_HI CBUS_REG_ADDR(VDIN0_MEAS_VS_COUNT_HI)
#define P_VDIN0_MEAS_VS_COUNT_LO CBUS_REG_ADDR(VDIN0_MEAS_VS_COUNT_LO)
#define P_VDIN0_MEAS_HS_RANGE CBUS_REG_ADDR(VDIN0_MEAS_HS_RANGE)
#define P_VDIN0_MEAS_HS_COUNT CBUS_REG_ADDR(VDIN0_MEAS_HS_COUNT)
#define P_VDIN0_BLKBAR_CTRL1 CBUS_REG_ADDR(VDIN0_BLKBAR_CTRL1)
#define P_VDIN0_BLKBAR_CTRL0 CBUS_REG_ADDR(VDIN0_BLKBAR_CTRL0)
#define P_VDIN0_BLKBAR_H_START_END CBUS_REG_ADDR(VDIN0_BLKBAR_H_START_END)
#define P_VDIN0_BLKBAR_V_START_END CBUS_REG_ADDR(VDIN0_BLKBAR_V_START_END)
#define P_VDIN0_BLKBAR_CNT_THRESHOLD CBUS_REG_ADDR(VDIN0_BLKBAR_CNT_THRESHOLD)
#define P_VDIN0_BLKBAR_ROW_TH1_TH2 CBUS_REG_ADDR(VDIN0_BLKBAR_ROW_TH1_TH2)
#define P_VDIN0_BLKBAR_IND_LEFT_START_END CBUS_REG_ADDR(VDIN0_BLKBAR_IND_LEFT_START_END)
#define P_VDIN0_BLKBAR_IND_RIGHT_START_END CBUS_REG_ADDR(VDIN0_BLKBAR_IND_RIGHT_START_END)
#define P_VDIN0_BLKBAR_IND_LEFT1_CNT CBUS_REG_ADDR(VDIN0_BLKBAR_IND_LEFT1_CNT)
#define P_VDIN0_BLKBAR_IND_LEFT2_CNT CBUS_REG_ADDR(VDIN0_BLKBAR_IND_LEFT2_CNT)
#define P_VDIN0_BLKBAR_IND_RIGHT1_CNT CBUS_REG_ADDR(VDIN0_BLKBAR_IND_RIGHT1_CNT)
#define P_VDIN0_BLKBAR_IND_RIGHT2_CNT CBUS_REG_ADDR(VDIN0_BLKBAR_IND_RIGHT2_CNT)
#define P_VDIN0_BLKBAR_STATUS0 CBUS_REG_ADDR(VDIN0_BLKBAR_STATUS0)
#define P_VDIN0_BLKBAR_STATUS1 CBUS_REG_ADDR(VDIN0_BLKBAR_STATUS1)
#define P_VDIN0_WIN_H_START_END CBUS_REG_ADDR(VDIN0_WIN_H_START_END)
#define P_VDIN0_WIN_V_START_END CBUS_REG_ADDR(VDIN0_WIN_V_START_END)
#define P_VDIN0_ASFIFO_CTRL3 CBUS_REG_ADDR(VDIN0_ASFIFO_CTRL3)
#define P_VDIN1_SCALE_COEF_IDX CBUS_REG_ADDR(VDIN1_SCALE_COEF_IDX)
#define P_VDIN1_SCALE_COEF CBUS_REG_ADDR(VDIN1_SCALE_COEF)
#define P_VDIN1_COM_CTRL0 CBUS_REG_ADDR(VDIN1_COM_CTRL0)
#define P_VDIN1_ACTIVE_MAX_PIX_CNT_STATUS CBUS_REG_ADDR(VDIN1_ACTIVE_MAX_PIX_CNT_STATUS)
#define P_VDIN1_LCNT_STATUS CBUS_REG_ADDR(VDIN1_LCNT_STATUS)
#define P_VDIN1_COM_STATUS0 CBUS_REG_ADDR(VDIN1_COM_STATUS0)
#define P_VDIN1_COM_STATUS1 CBUS_REG_ADDR(VDIN1_COM_STATUS1)
#define P_VDIN1_LCNT_SHADOW_STATUS CBUS_REG_ADDR(VDIN1_LCNT_SHADOW_STATUS)
#define P_VDIN1_ASFIFO_CTRL0 CBUS_REG_ADDR(VDIN1_ASFIFO_CTRL0)
#define P_VDIN1_ASFIFO_CTRL1 CBUS_REG_ADDR(VDIN1_ASFIFO_CTRL1)
#define P_VDIN1_WIDTHM1I_WIDTHM1O CBUS_REG_ADDR(VDIN1_WIDTHM1I_WIDTHM1O)
#define P_VDIN1_SC_MISC_CTRL CBUS_REG_ADDR(VDIN1_SC_MISC_CTRL)
#define P_VDIN1_HSC_PHASE_STEP CBUS_REG_ADDR(VDIN1_HSC_PHASE_STEP)
#define P_VDIN1_HSC_INI_CTRL CBUS_REG_ADDR(VDIN1_HSC_INI_CTRL)
#define P_VDIN1_COM_STATUS2 CBUS_REG_ADDR(VDIN1_COM_STATUS2)
#define P_VDIN1_ASFIFO_CTRL2 CBUS_REG_ADDR(VDIN1_ASFIFO_CTRL2)
#define P_VDIN1_MATRIX_CTRL CBUS_REG_ADDR(VDIN1_MATRIX_CTRL)
#define P_VDIN1_MATRIX_COEF00_01 CBUS_REG_ADDR(VDIN1_MATRIX_COEF00_01)
#define P_VDIN1_MATRIX_COEF02_10 CBUS_REG_ADDR(VDIN1_MATRIX_COEF02_10)
#define P_VDIN1_MATRIX_COEF11_12 CBUS_REG_ADDR(VDIN1_MATRIX_COEF11_12)
#define P_VDIN1_MATRIX_COEF20_21 CBUS_REG_ADDR(VDIN1_MATRIX_COEF20_21)
#define P_VDIN1_MATRIX_COEF22 CBUS_REG_ADDR(VDIN1_MATRIX_COEF22)
#define P_VDIN1_MATRIX_OFFSET0_1 CBUS_REG_ADDR(VDIN1_MATRIX_OFFSET0_1)
#define P_VDIN1_MATRIX_OFFSET2 CBUS_REG_ADDR(VDIN1_MATRIX_OFFSET2)
#define P_VDIN1_MATRIX_PRE_OFFSET0_1 CBUS_REG_ADDR(VDIN1_MATRIX_PRE_OFFSET0_1)
#define P_VDIN1_MATRIX_PRE_OFFSET2 CBUS_REG_ADDR(VDIN1_MATRIX_PRE_OFFSET2)
#define P_VDIN1_LFIFO_CTRL CBUS_REG_ADDR(VDIN1_LFIFO_CTRL)
#define P_VDIN1_COM_GCLK_CTRL CBUS_REG_ADDR(VDIN1_COM_GCLK_CTRL)
#define P_VDIN1_INTF_WIDTHM1 CBUS_REG_ADDR(VDIN1_INTF_WIDTHM1)
#define P_VDIN1_WR_CTRL2 CBUS_REG_ADDR(VDIN1_WR_CTRL2)
#define P_VDIN1_WR_CTRL CBUS_REG_ADDR(VDIN1_WR_CTRL)
#define P_VDIN1_WR_H_START_END CBUS_REG_ADDR(VDIN1_WR_H_START_END)
#define P_VDIN1_WR_V_START_END CBUS_REG_ADDR(VDIN1_WR_V_START_END)
#define P_VDIN1_VSC_PHASE_STEP CBUS_REG_ADDR(VDIN1_VSC_PHASE_STEP)
#define P_VDIN1_VSC_INI_CTRL CBUS_REG_ADDR(VDIN1_VSC_INI_CTRL)
#define P_VDIN1_SCIN_HEIGHTM1 CBUS_REG_ADDR(VDIN1_SCIN_HEIGHTM1)
#define P_VDIN1_DUMMY_DATA CBUS_REG_ADDR(VDIN1_DUMMY_DATA)
#define P_VDIN1_MATRIX_PROBE_COLOR CBUS_REG_ADDR(VDIN1_MATRIX_PROBE_COLOR)
#define P_VDIN1_MATRIX_HL_COLOR CBUS_REG_ADDR(VDIN1_MATRIX_HL_COLOR)
#define P_VDIN1_MATRIX_PROBE_POS CBUS_REG_ADDR(VDIN1_MATRIX_PROBE_POS)
#define P_VDIN1_CHROMA_ADDR_PORT CBUS_REG_ADDR(VDIN1_CHROMA_ADDR_PORT)
#define P_VDIN1_CHROMA_DATA_PORT CBUS_REG_ADDR(VDIN1_CHROMA_DATA_PORT)
#define P_VDIN1_CM_BRI_CON_CTRL CBUS_REG_ADDR(VDIN1_CM_BRI_CON_CTRL)
#define P_VDIN1_HIST_CTRL CBUS_REG_ADDR(VDIN1_HIST_CTRL)
#define P_VDIN1_HIST_H_START_END CBUS_REG_ADDR(VDIN1_HIST_H_START_END)
#define P_VDIN1_HIST_V_START_END CBUS_REG_ADDR(VDIN1_HIST_V_START_END)
#define P_VDIN1_HIST_MAX_MIN CBUS_REG_ADDR(VDIN1_HIST_MAX_MIN)
#define P_VDIN1_HIST_SPL_VAL CBUS_REG_ADDR(VDIN1_HIST_SPL_VAL)
#define P_VDIN1_HIST_SPL_PIX_CNT CBUS_REG_ADDR(VDIN1_HIST_SPL_PIX_CNT)
#define P_VDIN1_HIST_CHROMA_SUM CBUS_REG_ADDR(VDIN1_HIST_CHROMA_SUM)
#define P_VDIN1_DNLP_HIST00 CBUS_REG_ADDR(VDIN1_DNLP_HIST00)
#define P_VDIN1_DNLP_HIST01 CBUS_REG_ADDR(VDIN1_DNLP_HIST01)
#define P_VDIN1_DNLP_HIST02 CBUS_REG_ADDR(VDIN1_DNLP_HIST02)
#define P_VDIN1_DNLP_HIST03 CBUS_REG_ADDR(VDIN1_DNLP_HIST03)
#define P_VDIN1_DNLP_HIST04 CBUS_REG_ADDR(VDIN1_DNLP_HIST04)
#define P_VDIN1_DNLP_HIST05 CBUS_REG_ADDR(VDIN1_DNLP_HIST05)
#define P_VDIN1_DNLP_HIST06 CBUS_REG_ADDR(VDIN1_DNLP_HIST06)
#define P_VDIN1_DNLP_HIST07 CBUS_REG_ADDR(VDIN1_DNLP_HIST07)
#define P_VDIN1_DNLP_HIST08 CBUS_REG_ADDR(VDIN1_DNLP_HIST08)
#define P_VDIN1_DNLP_HIST09 CBUS_REG_ADDR(VDIN1_DNLP_HIST09)
#define P_VDIN1_DNLP_HIST10 CBUS_REG_ADDR(VDIN1_DNLP_HIST10)
#define P_VDIN1_DNLP_HIST11 CBUS_REG_ADDR(VDIN1_DNLP_HIST11)
#define P_VDIN1_DNLP_HIST12 CBUS_REG_ADDR(VDIN1_DNLP_HIST12)
#define P_VDIN1_DNLP_HIST13 CBUS_REG_ADDR(VDIN1_DNLP_HIST13)
#define P_VDIN1_DNLP_HIST14 CBUS_REG_ADDR(VDIN1_DNLP_HIST14)
#define P_VDIN1_DNLP_HIST15 CBUS_REG_ADDR(VDIN1_DNLP_HIST15)
#define P_VDIN1_DNLP_HIST16 CBUS_REG_ADDR(VDIN1_DNLP_HIST16)
#define P_VDIN1_DNLP_HIST17 CBUS_REG_ADDR(VDIN1_DNLP_HIST17)
#define P_VDIN1_DNLP_HIST18 CBUS_REG_ADDR(VDIN1_DNLP_HIST18)
#define P_VDIN1_DNLP_HIST19 CBUS_REG_ADDR(VDIN1_DNLP_HIST19)
#define P_VDIN1_DNLP_HIST20 CBUS_REG_ADDR(VDIN1_DNLP_HIST20)
#define P_VDIN1_DNLP_HIST21 CBUS_REG_ADDR(VDIN1_DNLP_HIST21)
#define P_VDIN1_DNLP_HIST22 CBUS_REG_ADDR(VDIN1_DNLP_HIST22)
#define P_VDIN1_DNLP_HIST23 CBUS_REG_ADDR(VDIN1_DNLP_HIST23)
#define P_VDIN1_DNLP_HIST24 CBUS_REG_ADDR(VDIN1_DNLP_HIST24)
#define P_VDIN1_DNLP_HIST25 CBUS_REG_ADDR(VDIN1_DNLP_HIST25)
#define P_VDIN1_DNLP_HIST26 CBUS_REG_ADDR(VDIN1_DNLP_HIST26)
#define P_VDIN1_DNLP_HIST27 CBUS_REG_ADDR(VDIN1_DNLP_HIST27)
#define P_VDIN1_DNLP_HIST28 CBUS_REG_ADDR(VDIN1_DNLP_HIST28)
#define P_VDIN1_DNLP_HIST29 CBUS_REG_ADDR(VDIN1_DNLP_HIST29)
#define P_VDIN1_DNLP_HIST30 CBUS_REG_ADDR(VDIN1_DNLP_HIST30)
#define P_VDIN1_DNLP_HIST31 CBUS_REG_ADDR(VDIN1_DNLP_HIST31)
#define P_VDIN1_LDIM_STTS_HIST_REGION_IDX CBUS_REG_ADDR(VDIN1_LDIM_STTS_HIST_REGION_IDX)
#define P_VDIN1_LDIM_STTS_HIST_SET_REGION CBUS_REG_ADDR(VDIN1_LDIM_STTS_HIST_SET_REGION)
#define P_VDIN1_LDIM_STTS_HIST_READ_REGION CBUS_REG_ADDR(VDIN1_LDIM_STTS_HIST_READ_REGION)
#define P_VDIN1_MEAS_CTRL0 CBUS_REG_ADDR(VDIN1_MEAS_CTRL0)
#define P_VDIN1_MEAS_VS_COUNT_HI CBUS_REG_ADDR(VDIN1_MEAS_VS_COUNT_HI)
#define P_VDIN1_MEAS_VS_COUNT_LO CBUS_REG_ADDR(VDIN1_MEAS_VS_COUNT_LO)
#define P_VDIN1_MEAS_HS_RANGE CBUS_REG_ADDR(VDIN1_MEAS_HS_RANGE)
#define P_VDIN1_MEAS_HS_COUNT CBUS_REG_ADDR(VDIN1_MEAS_HS_COUNT)
#define P_VDIN1_BLKBAR_CTRL1 CBUS_REG_ADDR(VDIN1_BLKBAR_CTRL1)
#define P_VDIN1_BLKBAR_CTRL0 CBUS_REG_ADDR(VDIN1_BLKBAR_CTRL0)
#define P_VDIN1_BLKBAR_H_START_END CBUS_REG_ADDR(VDIN1_BLKBAR_H_START_END)
#define P_VDIN1_BLKBAR_V_START_END CBUS_REG_ADDR(VDIN1_BLKBAR_V_START_END)
#define P_VDIN1_BLKBAR_CNT_THRESHOLD CBUS_REG_ADDR(VDIN1_BLKBAR_CNT_THRESHOLD)
#define P_VDIN1_BLKBAR_ROW_TH1_TH2 CBUS_REG_ADDR(VDIN1_BLKBAR_ROW_TH1_TH2)
#define P_VDIN1_BLKBAR_IND_LEFT_START_END CBUS_REG_ADDR(VDIN1_BLKBAR_IND_LEFT_START_END)
#define P_VDIN1_BLKBAR_IND_RIGHT_START_END CBUS_REG_ADDR(VDIN1_BLKBAR_IND_RIGHT_START_END)
#define P_VDIN1_BLKBAR_IND_LEFT1_CNT CBUS_REG_ADDR(VDIN1_BLKBAR_IND_LEFT1_CNT)
#define P_VDIN1_BLKBAR_IND_LEFT2_CNT CBUS_REG_ADDR(VDIN1_BLKBAR_IND_LEFT2_CNT)
#define P_VDIN1_BLKBAR_IND_RIGHT1_CNT CBUS_REG_ADDR(VDIN1_BLKBAR_IND_RIGHT1_CNT)
#define P_VDIN1_BLKBAR_IND_RIGHT2_CNT CBUS_REG_ADDR(VDIN1_BLKBAR_IND_RIGHT2_CNT)
#define P_VDIN1_BLKBAR_STATUS0 CBUS_REG_ADDR(VDIN1_BLKBAR_STATUS0)
#define P_VDIN1_BLKBAR_STATUS1 CBUS_REG_ADDR(VDIN1_BLKBAR_STATUS1)
#define P_VDIN1_WIN_H_START_END CBUS_REG_ADDR(VDIN1_WIN_H_START_END)
#define P_VDIN1_WIN_V_START_END CBUS_REG_ADDR(VDIN1_WIN_V_START_END)
#define P_VDIN1_ASFIFO_CTRL3 CBUS_REG_ADDR(VDIN1_ASFIFO_CTRL3)
#define P_VPP_DUMMY_DATA VPU_REG_ADDR(VPP_DUMMY_DATA)
#define P_VPP_LINE_IN_LENGTH VPU_REG_ADDR(VPP_LINE_IN_LENGTH)
#define P_VPP_PIC_IN_HEIGHT VPU_REG_ADDR(VPP_PIC_IN_HEIGHT)
#define P_VPP_SCALE_COEF_IDX VPU_REG_ADDR(VPP_SCALE_COEF_IDX)
#define P_VPP_SCALE_COEF VPU_REG_ADDR(VPP_SCALE_COEF)
#define P_VPP_VSC_REGION12_STARTP VPU_REG_ADDR(VPP_VSC_REGION12_STARTP)
#define P_VPP_VSC_REGION34_STARTP VPU_REG_ADDR(VPP_VSC_REGION34_STARTP)
#define P_VPP_VSC_REGION4_ENDP VPU_REG_ADDR(VPP_VSC_REGION4_ENDP)
#define P_VPP_VSC_START_PHASE_STEP VPU_REG_ADDR(VPP_VSC_START_PHASE_STEP)
#define P_VPP_VSC_REGION0_PHASE_SLOPE VPU_REG_ADDR(VPP_VSC_REGION0_PHASE_SLOPE)
#define P_VPP_VSC_REGION1_PHASE_SLOPE VPU_REG_ADDR(VPP_VSC_REGION1_PHASE_SLOPE)
#define P_VPP_VSC_REGION3_PHASE_SLOPE VPU_REG_ADDR(VPP_VSC_REGION3_PHASE_SLOPE)
#define P_VPP_VSC_REGION4_PHASE_SLOPE VPU_REG_ADDR(VPP_VSC_REGION4_PHASE_SLOPE)
#define P_VPP_VSC_PHASE_CTRL VPU_REG_ADDR(VPP_VSC_PHASE_CTRL)
#define P_VPP_VSC_INI_PHASE VPU_REG_ADDR(VPP_VSC_INI_PHASE)
#define P_VPP_HSC_REGION12_STARTP VPU_REG_ADDR(VPP_HSC_REGION12_STARTP)
#define P_VPP_HSC_REGION34_STARTP VPU_REG_ADDR(VPP_HSC_REGION34_STARTP)
#define P_VPP_HSC_REGION4_ENDP VPU_REG_ADDR(VPP_HSC_REGION4_ENDP)
#define P_VPP_HSC_START_PHASE_STEP VPU_REG_ADDR(VPP_HSC_START_PHASE_STEP)
#define P_VPP_HSC_REGION0_PHASE_SLOPE VPU_REG_ADDR(VPP_HSC_REGION0_PHASE_SLOPE)
#define P_VPP_HSC_REGION1_PHASE_SLOPE VPU_REG_ADDR(VPP_HSC_REGION1_PHASE_SLOPE)
#define P_VPP_HSC_REGION3_PHASE_SLOPE VPU_REG_ADDR(VPP_HSC_REGION3_PHASE_SLOPE)
#define P_VPP_HSC_REGION4_PHASE_SLOPE VPU_REG_ADDR(VPP_HSC_REGION4_PHASE_SLOPE)
#define P_VPP_HSC_PHASE_CTRL VPU_REG_ADDR(VPP_HSC_PHASE_CTRL)
#define P_VPP_SC_MISC VPU_REG_ADDR(VPP_SC_MISC)
#define P_VPP_PREBLEND_VD1_H_START_END VPU_REG_ADDR(VPP_PREBLEND_VD1_H_START_END)
#define P_VPP_PREBLEND_VD1_V_START_END VPU_REG_ADDR(VPP_PREBLEND_VD1_V_START_END)
#define P_VPP_POSTBLEND_VD1_H_START_END VPU_REG_ADDR(VPP_POSTBLEND_VD1_H_START_END)
#define P_VPP_POSTBLEND_VD1_V_START_END VPU_REG_ADDR(VPP_POSTBLEND_VD1_V_START_END)
#define P_VPP_BLEND_VD2_H_START_END VPU_REG_ADDR(VPP_BLEND_VD2_H_START_END)
#define P_VPP_BLEND_VD2_V_START_END VPU_REG_ADDR(VPP_BLEND_VD2_V_START_END)
#define P_VPP_PREBLEND_H_SIZE VPU_REG_ADDR(VPP_PREBLEND_H_SIZE)
#define P_VPP_POSTBLEND_H_SIZE VPU_REG_ADDR(VPP_POSTBLEND_H_SIZE)
#define P_VPP_HOLD_LINES VPU_REG_ADDR(VPP_HOLD_LINES)
#define P_VPP_BLEND_ONECOLOR_CTRL VPU_REG_ADDR(VPP_BLEND_ONECOLOR_CTRL)
#define P_VPP_PREBLEND_CURRENT_XY VPU_REG_ADDR(VPP_PREBLEND_CURRENT_XY)
#define P_VPP_POSTBLEND_CURRENT_XY VPU_REG_ADDR(VPP_POSTBLEND_CURRENT_XY)
#define P_VPP_MISC VPU_REG_ADDR(VPP_MISC)
#define P_VPP_OFIFO_SIZE VPU_REG_ADDR(VPP_OFIFO_SIZE)
#define P_VPP_FIFO_STATUS VPU_REG_ADDR(VPP_FIFO_STATUS)
#define P_VPP_SMOKE_CTRL VPU_REG_ADDR(VPP_SMOKE_CTRL)
#define P_VPP_SMOKE1_VAL VPU_REG_ADDR(VPP_SMOKE1_VAL)
#define P_VPP_SMOKE2_VAL VPU_REG_ADDR(VPP_SMOKE2_VAL)
#define P_VPP_SMOKE3_VAL VPU_REG_ADDR(VPP_SMOKE3_VAL)
#define P_VPP_SMOKE1_H_START_END VPU_REG_ADDR(VPP_SMOKE1_H_START_END)
#define P_VPP_SMOKE1_V_START_END VPU_REG_ADDR(VPP_SMOKE1_V_START_END)
#define P_VPP_SMOKE2_H_START_END VPU_REG_ADDR(VPP_SMOKE2_H_START_END)
#define P_VPP_SMOKE2_V_START_END VPU_REG_ADDR(VPP_SMOKE2_V_START_END)
#define P_VPP_SMOKE3_H_START_END VPU_REG_ADDR(VPP_SMOKE3_H_START_END)
#define P_VPP_SMOKE3_V_START_END VPU_REG_ADDR(VPP_SMOKE3_V_START_END)
#define P_VPP_SCO_FIFO_CTRL VPU_REG_ADDR(VPP_SCO_FIFO_CTRL)
#define P_VPP_HSC_PHASE_CTRL1 VPU_REG_ADDR(VPP_HSC_PHASE_CTRL1)
#define P_VPP_HSC_INI_PAT_CTRL VPU_REG_ADDR(VPP_HSC_INI_PAT_CTRL)
#define P_VPP_VADJ_CTRL VPU_REG_ADDR(VPP_VADJ_CTRL)
#define P_VPP_VADJ1_Y VPU_REG_ADDR(VPP_VADJ1_Y)
#define P_VPP_VADJ1_MA_MB VPU_REG_ADDR(VPP_VADJ1_MA_MB)
#define P_VPP_VADJ1_MC_MD VPU_REG_ADDR(VPP_VADJ1_MC_MD)
#define P_VPP_VADJ2_Y VPU_REG_ADDR(VPP_VADJ2_Y)
#define P_VPP_VADJ2_MA_MB VPU_REG_ADDR(VPP_VADJ2_MA_MB)
#define P_VPP_VADJ2_MC_MD VPU_REG_ADDR(VPP_VADJ2_MC_MD)
#define P_VPP_HSHARP_CTRL VPU_REG_ADDR(VPP_HSHARP_CTRL)
#define P_VPP_HSHARP_LUMA_THRESH01 VPU_REG_ADDR(VPP_HSHARP_LUMA_THRESH01)
#define P_VPP_HSHARP_LUMA_THRESH23 VPU_REG_ADDR(VPP_HSHARP_LUMA_THRESH23)
#define P_VPP_HSHARP_CHROMA_THRESH01 VPU_REG_ADDR(VPP_HSHARP_CHROMA_THRESH01)
#define P_VPP_HSHARP_CHROMA_THRESH23 VPU_REG_ADDR(VPP_HSHARP_CHROMA_THRESH23)
#define P_VPP_HSHARP_LUMA_GAIN VPU_REG_ADDR(VPP_HSHARP_LUMA_GAIN)
#define P_VPP_HSHARP_CHROMA_GAIN VPU_REG_ADDR(VPP_HSHARP_CHROMA_GAIN)
#define P_VPP_MATRIX_PROBE_COLOR VPU_REG_ADDR(VPP_MATRIX_PROBE_COLOR)
#define P_VPP_MATRIX_HL_COLOR VPU_REG_ADDR(VPP_MATRIX_HL_COLOR)
#define P_VPP_MATRIX_PROBE_POS VPU_REG_ADDR(VPP_MATRIX_PROBE_POS)
#define P_VPP_MATRIX_CTRL VPU_REG_ADDR(VPP_MATRIX_CTRL)
#define P_VPP_MATRIX_COEF00_01 VPU_REG_ADDR(VPP_MATRIX_COEF00_01)
#define P_VPP_MATRIX_COEF02_10 VPU_REG_ADDR(VPP_MATRIX_COEF02_10)
#define P_VPP_MATRIX_COEF11_12 VPU_REG_ADDR(VPP_MATRIX_COEF11_12)
#define P_VPP_MATRIX_COEF20_21 VPU_REG_ADDR(VPP_MATRIX_COEF20_21)
#define P_VPP_MATRIX_COEF22 VPU_REG_ADDR(VPP_MATRIX_COEF22)
#define P_VPP_MATRIX_OFFSET0_1 VPU_REG_ADDR(VPP_MATRIX_OFFSET0_1)
#define P_VPP_MATRIX_OFFSET2 VPU_REG_ADDR(VPP_MATRIX_OFFSET2)
#define P_VPP_MATRIX_PRE_OFFSET0_1 VPU_REG_ADDR(VPP_MATRIX_PRE_OFFSET0_1)
#define P_VPP_MATRIX_PRE_OFFSET2 VPU_REG_ADDR(VPP_MATRIX_PRE_OFFSET2)
#define P_VPP_DUMMY_DATA1 VPU_REG_ADDR(VPP_DUMMY_DATA1)
#define P_VPP_GAINOFF_CTRL0 VPU_REG_ADDR(VPP_GAINOFF_CTRL0)
#define P_VPP_GAINOFF_CTRL1 VPU_REG_ADDR(VPP_GAINOFF_CTRL1)
#define P_VPP_GAINOFF_CTRL2 VPU_REG_ADDR(VPP_GAINOFF_CTRL2)
#define P_VPP_GAINOFF_CTRL3 VPU_REG_ADDR(VPP_GAINOFF_CTRL3)
#define P_VPP_GAINOFF_CTRL4 VPU_REG_ADDR(VPP_GAINOFF_CTRL4)
#define P_VPP_CHROMA_ADDR_PORT VPU_REG_ADDR(VPP_CHROMA_ADDR_PORT)
#define P_VPP_CHROMA_DATA_PORT VPU_REG_ADDR(VPP_CHROMA_DATA_PORT)
#define P_VPP_GCLK_CTRL0 VPU_REG_ADDR(VPP_GCLK_CTRL0)
#define P_VPP_GCLK_CTRL1 VPU_REG_ADDR(VPP_GCLK_CTRL1)
#define P_VPP_SC_GCLK_CTRL VPU_REG_ADDR(VPP_SC_GCLK_CTRL)
#define P_VPP_MISC1 VPU_REG_ADDR(VPP_MISC1)
#define P_VPP_BLACKEXT_CTRL VPU_REG_ADDR(VPP_BLACKEXT_CTRL)
#define P_VPP_DNLP_CTRL_00 VPU_REG_ADDR(VPP_DNLP_CTRL_00)
#define P_VPP_DNLP_CTRL_01 VPU_REG_ADDR(VPP_DNLP_CTRL_01)
#define P_VPP_DNLP_CTRL_02 VPU_REG_ADDR(VPP_DNLP_CTRL_02)
#define P_VPP_DNLP_CTRL_03 VPU_REG_ADDR(VPP_DNLP_CTRL_03)
#define P_VPP_DNLP_CTRL_04 VPU_REG_ADDR(VPP_DNLP_CTRL_04)
#define P_VPP_DNLP_CTRL_05 VPU_REG_ADDR(VPP_DNLP_CTRL_05)
#define P_VPP_DNLP_CTRL_06 VPU_REG_ADDR(VPP_DNLP_CTRL_06)
#define P_VPP_DNLP_CTRL_07 VPU_REG_ADDR(VPP_DNLP_CTRL_07)
#define P_VPP_DNLP_CTRL_08 VPU_REG_ADDR(VPP_DNLP_CTRL_08)
#define P_VPP_DNLP_CTRL_09 VPU_REG_ADDR(VPP_DNLP_CTRL_09)
#define P_VPP_DNLP_CTRL_10 VPU_REG_ADDR(VPP_DNLP_CTRL_10)
#define P_VPP_DNLP_CTRL_11 VPU_REG_ADDR(VPP_DNLP_CTRL_11)
#define P_VPP_DNLP_CTRL_12 VPU_REG_ADDR(VPP_DNLP_CTRL_12)
#define P_VPP_DNLP_CTRL_13 VPU_REG_ADDR(VPP_DNLP_CTRL_13)
#define P_VPP_DNLP_CTRL_14 VPU_REG_ADDR(VPP_DNLP_CTRL_14)
#define P_VPP_DNLP_CTRL_15 VPU_REG_ADDR(VPP_DNLP_CTRL_15)
#define P_VPP_PEAKING_HGAIN VPU_REG_ADDR(VPP_PEAKING_HGAIN)
#define P_VPP_PEAKING_VGAIN VPU_REG_ADDR(VPP_PEAKING_VGAIN)
#define P_VPP_PEAKING_NLP_1 VPU_REG_ADDR(VPP_PEAKING_NLP_1)
#define P_VPP_PEAKING_NLP_2 VPU_REG_ADDR(VPP_PEAKING_NLP_2)
#define P_VPP_PEAKING_NLP_3 VPU_REG_ADDR(VPP_PEAKING_NLP_3)
#define P_VPP_PEAKING_NLP_4 VPU_REG_ADDR(VPP_PEAKING_NLP_4)
#define P_VPP_PEAKING_NLP_5 VPU_REG_ADDR(VPP_PEAKING_NLP_5)
#define P_VPP_SHARP_LIMIT VPU_REG_ADDR(VPP_SHARP_LIMIT)
#define P_VPP_VLTI_CTRL VPU_REG_ADDR(VPP_VLTI_CTRL)
#define P_VPP_HLTI_CTRL VPU_REG_ADDR(VPP_HLTI_CTRL)
#define P_VPP_CTI_CTRL VPU_REG_ADDR(VPP_CTI_CTRL)
#define P_VPP_BLUE_STRETCH_1 VPU_REG_ADDR(VPP_BLUE_STRETCH_1)
#define P_VPP_BLUE_STRETCH_2 VPU_REG_ADDR(VPP_BLUE_STRETCH_2)
#define P_VPP_BLUE_STRETCH_3 VPU_REG_ADDR(VPP_BLUE_STRETCH_3)
#define P_VPP_CCORING_CTRL VPU_REG_ADDR(VPP_CCORING_CTRL)
#define P_VPP_VE_ENABLE_CTRL VPU_REG_ADDR(VPP_VE_ENABLE_CTRL)
#define P_VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH VPU_REG_ADDR(VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH)
#define P_VPP_VE_DEMO_CENTER_BAR VPU_REG_ADDR(VPP_VE_DEMO_CENTER_BAR)
#define P_VPP_VE_H_V_SIZE VPU_REG_ADDR(VPP_VE_H_V_SIZE)
#define P_VPP_VDO_MEAS_CTRL VPU_REG_ADDR(VPP_VDO_MEAS_CTRL)
#define P_VPP_VDO_MEAS_VS_COUNT_HI VPU_REG_ADDR(VPP_VDO_MEAS_VS_COUNT_HI)
#define P_VPP_VDO_MEAS_VS_COUNT_LO VPU_REG_ADDR(VPP_VDO_MEAS_VS_COUNT_LO)
#define P_VPP_INPUT_CTRL VPU_REG_ADDR(VPP_INPUT_CTRL)
#define P_VPP_CTI_CTRL2 VPU_REG_ADDR(VPP_CTI_CTRL2)
#define P_VPP_PEAKING_SAT_THD1 VPU_REG_ADDR(VPP_PEAKING_SAT_THD1)
#define P_VPP_PEAKING_SAT_THD2 VPU_REG_ADDR(VPP_PEAKING_SAT_THD2)
#define P_VPP_PEAKING_SAT_THD3 VPU_REG_ADDR(VPP_PEAKING_SAT_THD3)
#define P_VPP_PEAKING_SAT_THD4 VPU_REG_ADDR(VPP_PEAKING_SAT_THD4)
#define P_VPP_PEAKING_SAT_THD5 VPU_REG_ADDR(VPP_PEAKING_SAT_THD5)
#define P_VPP_PEAKING_SAT_THD6 VPU_REG_ADDR(VPP_PEAKING_SAT_THD6)
#define P_VPP_PEAKING_SAT_THD7 VPU_REG_ADDR(VPP_PEAKING_SAT_THD7)
#define P_VPP_PEAKING_SAT_THD8 VPU_REG_ADDR(VPP_PEAKING_SAT_THD8)
#define P_VPP_PEAKING_SAT_THD9 VPU_REG_ADDR(VPP_PEAKING_SAT_THD9)
#define P_VPP_PEAKING_GAIN_ADD1 VPU_REG_ADDR(VPP_PEAKING_GAIN_ADD1)
#define P_VPP_PEAKING_GAIN_ADD2 VPU_REG_ADDR(VPP_PEAKING_GAIN_ADD2)
#define P_VPP_PEAKING_DNLP VPU_REG_ADDR(VPP_PEAKING_DNLP)
#define P_VPP_SHARP_DEMO_WIN_CTRL1 VPU_REG_ADDR(VPP_SHARP_DEMO_WIN_CTRL1)
#define P_VPP_SHARP_DEMO_WIN_CTRL2 VPU_REG_ADDR(VPP_SHARP_DEMO_WIN_CTRL2)
#define P_VPP_FRONT_HLTI_CTRL VPU_REG_ADDR(VPP_FRONT_HLTI_CTRL)
#define P_VPP_FRONT_CTI_CTRL VPU_REG_ADDR(VPP_FRONT_CTI_CTRL)
#define P_VPP_FRONT_CTI_CTRL2 VPU_REG_ADDR(VPP_FRONT_CTI_CTRL2)
#define P_VPP_OSD_VSC_PHASE_STEP VPU_REG_ADDR(VPP_OSD_VSC_PHASE_STEP)
#define P_VPP_OSD_VSC_INI_PHASE VPU_REG_ADDR(VPP_OSD_VSC_INI_PHASE)
#define P_VPP_OSD_VSC_CTRL0 VPU_REG_ADDR(VPP_OSD_VSC_CTRL0)
#define P_VPP_OSD_HSC_PHASE_STEP VPU_REG_ADDR(VPP_OSD_HSC_PHASE_STEP)
#define P_VPP_OSD_HSC_INI_PHASE VPU_REG_ADDR(VPP_OSD_HSC_INI_PHASE)
#define P_VPP_OSD_HSC_CTRL0 VPU_REG_ADDR(VPP_OSD_HSC_CTRL0)
#define P_VPP_OSD_HSC_INI_PAT_CTRL VPU_REG_ADDR(VPP_OSD_HSC_INI_PAT_CTRL)
#define P_VPP_OSD_SC_DUMMY_DATA VPU_REG_ADDR(VPP_OSD_SC_DUMMY_DATA)
#define P_VPP_OSD_SC_CTRL0 VPU_REG_ADDR(VPP_OSD_SC_CTRL0)
#define P_VPP_OSD_SCI_WH_M1 VPU_REG_ADDR(VPP_OSD_SCI_WH_M1)
#define P_VPP_OSD_SCO_H_START_END VPU_REG_ADDR(VPP_OSD_SCO_H_START_END)
#define P_VPP_OSD_SCO_V_START_END VPU_REG_ADDR(VPP_OSD_SCO_V_START_END)
#define P_VPP_OSD_SCALE_COEF_IDX VPU_REG_ADDR(VPP_OSD_SCALE_COEF_IDX)
#define P_VPP_OSD_SCALE_COEF VPU_REG_ADDR(VPP_OSD_SCALE_COEF)
#define P_VPP_INT_LINE_NUM VPU_REG_ADDR(VPP_INT_LINE_NUM)
#define P_VPP2_DUMMY_DATA VPU_REG_ADDR(VPP2_DUMMY_DATA)
#define P_VPP2_LINE_IN_LENGTH VPU_REG_ADDR(VPP2_LINE_IN_LENGTH)
#define P_VPP2_PIC_IN_HEIGHT VPU_REG_ADDR(VPP2_PIC_IN_HEIGHT)
#define P_VPP2_SCALE_COEF_IDX VPU_REG_ADDR(VPP2_SCALE_COEF_IDX)
#define P_VPP2_SCALE_COEF VPU_REG_ADDR(VPP2_SCALE_COEF)
#define P_VPP2_VSC_REGION12_STARTP VPU_REG_ADDR(VPP2_VSC_REGION12_STARTP)
#define P_VPP2_VSC_REGION34_STARTP VPU_REG_ADDR(VPP2_VSC_REGION34_STARTP)
#define P_VPP2_VSC_REGION4_ENDP VPU_REG_ADDR(VPP2_VSC_REGION4_ENDP)
#define P_VPP2_VSC_START_PHASE_STEP VPU_REG_ADDR(VPP2_VSC_START_PHASE_STEP)
#define P_VPP2_VSC_REGION0_PHASE_SLOPE VPU_REG_ADDR(VPP2_VSC_REGION0_PHASE_SLOPE)
#define P_VPP2_VSC_REGION1_PHASE_SLOPE VPU_REG_ADDR(VPP2_VSC_REGION1_PHASE_SLOPE)
#define P_VPP2_VSC_REGION3_PHASE_SLOPE VPU_REG_ADDR(VPP2_VSC_REGION3_PHASE_SLOPE)
#define P_VPP2_VSC_REGION4_PHASE_SLOPE VPU_REG_ADDR(VPP2_VSC_REGION4_PHASE_SLOPE)
#define P_VPP2_VSC_PHASE_CTRL VPU_REG_ADDR(VPP2_VSC_PHASE_CTRL)
#define P_VPP2_VSC_INI_PHASE VPU_REG_ADDR(VPP2_VSC_INI_PHASE)
#define P_VPP2_HSC_REGION12_STARTP VPU_REG_ADDR(VPP2_HSC_REGION12_STARTP)
#define P_VPP2_HSC_REGION34_STARTP VPU_REG_ADDR(VPP2_HSC_REGION34_STARTP)
#define P_VPP2_HSC_REGION4_ENDP VPU_REG_ADDR(VPP2_HSC_REGION4_ENDP)
#define P_VPP2_HSC_START_PHASE_STEP VPU_REG_ADDR(VPP2_HSC_START_PHASE_STEP)
#define P_VPP2_HSC_REGION0_PHASE_SLOPE VPU_REG_ADDR(VPP2_HSC_REGION0_PHASE_SLOPE)
#define P_VPP2_HSC_REGION1_PHASE_SLOPE VPU_REG_ADDR(VPP2_HSC_REGION1_PHASE_SLOPE)
#define P_VPP2_HSC_REGION3_PHASE_SLOPE VPU_REG_ADDR(VPP2_HSC_REGION3_PHASE_SLOPE)
#define P_VPP2_HSC_REGION4_PHASE_SLOPE VPU_REG_ADDR(VPP2_HSC_REGION4_PHASE_SLOPE)
#define P_VPP2_HSC_PHASE_CTRL VPU_REG_ADDR(VPP2_HSC_PHASE_CTRL)
#define P_VPP2_SC_MISC VPU_REG_ADDR(VPP2_SC_MISC)
#define P_VPP2_PREBLEND_VD1_H_START_END VPU_REG_ADDR(VPP2_PREBLEND_VD1_H_START_END)
#define P_VPP2_PREBLEND_VD1_V_START_END VPU_REG_ADDR(VPP2_PREBLEND_VD1_V_START_END)
#define P_VPP2_POSTBLEND_VD1_H_START_END VPU_REG_ADDR(VPP2_POSTBLEND_VD1_H_START_END)
#define P_VPP2_POSTBLEND_VD1_V_START_END VPU_REG_ADDR(VPP2_POSTBLEND_VD1_V_START_END)
#define P_VPP2_PREBLEND_H_SIZE VPU_REG_ADDR(VPP2_PREBLEND_H_SIZE)
#define P_VPP2_POSTBLEND_H_SIZE VPU_REG_ADDR(VPP2_POSTBLEND_H_SIZE)
#define P_VPP2_HOLD_LINES VPU_REG_ADDR(VPP2_HOLD_LINES)
#define P_VPP2_BLEND_ONECOLOR_CTRL VPU_REG_ADDR(VPP2_BLEND_ONECOLOR_CTRL)
#define P_VPP2_PREBLEND_CURRENT_XY VPU_REG_ADDR(VPP2_PREBLEND_CURRENT_XY)
#define P_VPP2_POSTBLEND_CURRENT_XY VPU_REG_ADDR(VPP2_POSTBLEND_CURRENT_XY)
#define P_VPP2_MISC VPU_REG_ADDR(VPP2_MISC)
#define P_VPP2_OFIFO_SIZE VPU_REG_ADDR(VPP2_OFIFO_SIZE)
#define P_VPP2_FIFO_STATUS VPU_REG_ADDR(VPP2_FIFO_STATUS)
#define P_VPP2_SMOKE_CTRL VPU_REG_ADDR(VPP2_SMOKE_CTRL)
#define P_VPP2_SMOKE1_VAL VPU_REG_ADDR(VPP2_SMOKE1_VAL)
#define P_VPP2_SMOKE2_VAL VPU_REG_ADDR(VPP2_SMOKE2_VAL)
#define P_VPP2_SMOKE1_H_START_END VPU_REG_ADDR(VPP2_SMOKE1_H_START_END)
#define P_VPP2_SMOKE1_V_START_END VPU_REG_ADDR(VPP2_SMOKE1_V_START_END)
#define P_VPP2_SMOKE2_H_START_END VPU_REG_ADDR(VPP2_SMOKE2_H_START_END)
#define P_VPP2_SMOKE2_V_START_END VPU_REG_ADDR(VPP2_SMOKE2_V_START_END)
#define P_VPP2_SCO_FIFO_CTRL VPU_REG_ADDR(VPP2_SCO_FIFO_CTRL)
#define P_VPP2_HSC_PHASE_CTRL1 VPU_REG_ADDR(VPP2_HSC_PHASE_CTRL1)
#define P_VPP2_HSC_INI_PAT_CTRL VPU_REG_ADDR(VPP2_HSC_INI_PAT_CTRL)
#define P_VPP2_VADJ_CTRL VPU_REG_ADDR(VPP2_VADJ_CTRL)
#define P_VPP2_VADJ1_Y VPU_REG_ADDR(VPP2_VADJ1_Y)
#define P_VPP2_VADJ1_MA_MB VPU_REG_ADDR(VPP2_VADJ1_MA_MB)
#define P_VPP2_VADJ1_MC_MD VPU_REG_ADDR(VPP2_VADJ1_MC_MD)
#define P_VPP2_VADJ2_Y VPU_REG_ADDR(VPP2_VADJ2_Y)
#define P_VPP2_VADJ2_MA_MB VPU_REG_ADDR(VPP2_VADJ2_MA_MB)
#define P_VPP2_VADJ2_MC_MD VPU_REG_ADDR(VPP2_VADJ2_MC_MD)
#define P_VPP2_MATRIX_PROBE_COLOR VPU_REG_ADDR(VPP2_MATRIX_PROBE_COLOR)
#define P_VPP2_MATRIX_HL_COLOR VPU_REG_ADDR(VPP2_MATRIX_HL_COLOR)
#define P_VPP2_MATRIX_PROBE_POS VPU_REG_ADDR(VPP2_MATRIX_PROBE_POS)
#define P_VPP2_MATRIX_CTRL VPU_REG_ADDR(VPP2_MATRIX_CTRL)
#define P_VPP2_MATRIX_COEF00_01 VPU_REG_ADDR(VPP2_MATRIX_COEF00_01)
#define P_VPP2_MATRIX_COEF02_10 VPU_REG_ADDR(VPP2_MATRIX_COEF02_10)
#define P_VPP2_MATRIX_COEF11_12 VPU_REG_ADDR(VPP2_MATRIX_COEF11_12)
#define P_VPP2_MATRIX_COEF20_21 VPU_REG_ADDR(VPP2_MATRIX_COEF20_21)
#define P_VPP2_MATRIX_COEF22 VPU_REG_ADDR(VPP2_MATRIX_COEF22)
#define P_VPP2_MATRIX_OFFSET0_1 VPU_REG_ADDR(VPP2_MATRIX_OFFSET0_1)
#define P_VPP2_MATRIX_OFFSET2 VPU_REG_ADDR(VPP2_MATRIX_OFFSET2)
#define P_VPP2_MATRIX_PRE_OFFSET0_1 VPU_REG_ADDR(VPP2_MATRIX_PRE_OFFSET0_1)
#define P_VPP2_MATRIX_PRE_OFFSET2 VPU_REG_ADDR(VPP2_MATRIX_PRE_OFFSET2)
#define P_VPP2_DUMMY_DATA1 VPU_REG_ADDR(VPP2_DUMMY_DATA1)
#define P_VPP2_GAINOFF_CTRL0 VPU_REG_ADDR(VPP2_GAINOFF_CTRL0)
#define P_VPP2_GAINOFF_CTRL1 VPU_REG_ADDR(VPP2_GAINOFF_CTRL1)
#define P_VPP2_GAINOFF_CTRL2 VPU_REG_ADDR(VPP2_GAINOFF_CTRL2)
#define P_VPP2_GAINOFF_CTRL3 VPU_REG_ADDR(VPP2_GAINOFF_CTRL3)
#define P_VPP2_GAINOFF_CTRL4 VPU_REG_ADDR(VPP2_GAINOFF_CTRL4)
#define P_VPP2_CHROMA_ADDR_PORT VPU_REG_ADDR(VPP2_CHROMA_ADDR_PORT)
#define P_VPP2_CHROMA_DATA_PORT VPU_REG_ADDR(VPP2_CHROMA_DATA_PORT)
#define P_VPP2_GCLK_CTRL0 VPU_REG_ADDR(VPP2_GCLK_CTRL0)
#define P_VPP2_GCLK_CTRL1 VPU_REG_ADDR(VPP2_GCLK_CTRL1)
#define P_VPP2_SC_GCLK_CTRL VPU_REG_ADDR(VPP2_SC_GCLK_CTRL)
#define P_VPP2_MISC1 VPU_REG_ADDR(VPP2_MISC1)
#define P_VPP2_DNLP_CTRL_00 VPU_REG_ADDR(VPP2_DNLP_CTRL_00)
#define P_VPP2_DNLP_CTRL_01 VPU_REG_ADDR(VPP2_DNLP_CTRL_01)
#define P_VPP2_DNLP_CTRL_02 VPU_REG_ADDR(VPP2_DNLP_CTRL_02)
#define P_VPP2_DNLP_CTRL_03 VPU_REG_ADDR(VPP2_DNLP_CTRL_03)
#define P_VPP2_DNLP_CTRL_04 VPU_REG_ADDR(VPP2_DNLP_CTRL_04)
#define P_VPP2_DNLP_CTRL_05 VPU_REG_ADDR(VPP2_DNLP_CTRL_05)
#define P_VPP2_DNLP_CTRL_06 VPU_REG_ADDR(VPP2_DNLP_CTRL_06)
#define P_VPP2_DNLP_CTRL_07 VPU_REG_ADDR(VPP2_DNLP_CTRL_07)
#define P_VPP2_DNLP_CTRL_08 VPU_REG_ADDR(VPP2_DNLP_CTRL_08)
#define P_VPP2_DNLP_CTRL_09 VPU_REG_ADDR(VPP2_DNLP_CTRL_09)
#define P_VPP2_DNLP_CTRL_10 VPU_REG_ADDR(VPP2_DNLP_CTRL_10)
#define P_VPP2_DNLP_CTRL_11 VPU_REG_ADDR(VPP2_DNLP_CTRL_11)
#define P_VPP2_DNLP_CTRL_12 VPU_REG_ADDR(VPP2_DNLP_CTRL_12)
#define P_VPP2_DNLP_CTRL_13 VPU_REG_ADDR(VPP2_DNLP_CTRL_13)
#define P_VPP2_DNLP_CTRL_14 VPU_REG_ADDR(VPP2_DNLP_CTRL_14)
#define P_VPP2_DNLP_CTRL_15 VPU_REG_ADDR(VPP2_DNLP_CTRL_15)
#define P_VPP2_VE_ENABLE_CTRL VPU_REG_ADDR(VPP2_VE_ENABLE_CTRL)
#define P_VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH VPU_REG_ADDR(VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH)
#define P_VPP2_VE_DEMO_CENTER_BAR VPU_REG_ADDR(VPP2_VE_DEMO_CENTER_BAR)
#define P_VPP2_VE_H_V_SIZE VPU_REG_ADDR(VPP2_VE_H_V_SIZE)
#define P_VPP2_VDO_MEAS_CTRL VPU_REG_ADDR(VPP2_VDO_MEAS_CTRL)
#define P_VPP2_VDO_MEAS_VS_COUNT_HI VPU_REG_ADDR(VPP2_VDO_MEAS_VS_COUNT_HI)
#define P_VPP2_VDO_MEAS_VS_COUNT_LO VPU_REG_ADDR(VPP2_VDO_MEAS_VS_COUNT_LO)
#define P_VPP2_OSD_VSC_PHASE_STEP VPU_REG_ADDR(VPP2_OSD_VSC_PHASE_STEP)
#define P_VPP2_OSD_VSC_INI_PHASE VPU_REG_ADDR(VPP2_OSD_VSC_INI_PHASE)
#define P_VPP2_OSD_VSC_CTRL0 VPU_REG_ADDR(VPP2_OSD_VSC_CTRL0)
#define P_VPP2_OSD_HSC_PHASE_STEP VPU_REG_ADDR(VPP2_OSD_HSC_PHASE_STEP)
#define P_VPP2_OSD_HSC_INI_PHASE VPU_REG_ADDR(VPP2_OSD_HSC_INI_PHASE)
#define P_VPP2_OSD_HSC_CTRL0 VPU_REG_ADDR(VPP2_OSD_HSC_CTRL0)
#define P_VPP2_OSD_HSC_INI_PAT_CTRL VPU_REG_ADDR(VPP2_OSD_HSC_INI_PAT_CTRL)
#define P_VPP2_OSD_SC_DUMMY_DATA VPU_REG_ADDR(VPP2_OSD_SC_DUMMY_DATA)
#define P_VPP2_OSD_SC_CTRL0 VPU_REG_ADDR(VPP2_OSD_SC_CTRL0)
#define P_VPP2_OSD_SCI_WH_M1 VPU_REG_ADDR(VPP2_OSD_SCI_WH_M1)
#define P_VPP2_OSD_SCO_H_START_END VPU_REG_ADDR(VPP2_OSD_SCO_H_START_END)
#define P_VPP2_OSD_SCO_V_START_END VPU_REG_ADDR(VPP2_OSD_SCO_V_START_END)
#define P_VPP2_OSD_SCALE_COEF_IDX VPU_REG_ADDR(VPP2_OSD_SCALE_COEF_IDX)
#define P_VPP2_OSD_SCALE_COEF VPU_REG_ADDR(VPP2_OSD_SCALE_COEF)
#define P_VPP2_INT_LINE_NUM VPU_REG_ADDR(VPP2_INT_LINE_NUM)
#define P_VIU_ADDR_START VPU_REG_ADDR(VIU_ADDR_START)
#define P_VIU_ADDR_END VPU_REG_ADDR(VIU_ADDR_END)
#define P_VIU_SW_RESET VPU_REG_ADDR(VIU_SW_RESET)
#define P_VIU_MISC_CTRL0 VPU_REG_ADDR(VIU_MISC_CTRL0)
#define P_D2D3_INTF_LENGTH VPU_REG_ADDR(D2D3_INTF_LENGTH)
#define P_D2D3_INTF_CTRL0 VPU_REG_ADDR(D2D3_INTF_CTRL0)
#define P_VIU_OSD1_CTRL_STAT VPU_REG_ADDR(VIU_OSD1_CTRL_STAT)
#define P_VIU_OSD1_CTRL_STAT2 VPU_REG_ADDR(VIU_OSD1_CTRL_STAT2)
#define P_VIU_OSD1_COLOR_ADDR VPU_REG_ADDR(VIU_OSD1_COLOR_ADDR)
#define P_VIU_OSD1_COLOR VPU_REG_ADDR(VIU_OSD1_COLOR)
#define P_VIU_OSD1_TCOLOR_AG0 VPU_REG_ADDR(VIU_OSD1_TCOLOR_AG0)
#define P_VIU_OSD1_TCOLOR_AG1 VPU_REG_ADDR(VIU_OSD1_TCOLOR_AG1)
#define P_VIU_OSD1_TCOLOR_AG2 VPU_REG_ADDR(VIU_OSD1_TCOLOR_AG2)
#define P_VIU_OSD1_TCOLOR_AG3 VPU_REG_ADDR(VIU_OSD1_TCOLOR_AG3)
#define P_VIU_OSD1_BLK0_CFG_W0 VPU_REG_ADDR(VIU_OSD1_BLK0_CFG_W0)
#define P_VIU_OSD1_BLK1_CFG_W0 VPU_REG_ADDR(VIU_OSD1_BLK1_CFG_W0)
#define P_VIU_OSD1_BLK2_CFG_W0 VPU_REG_ADDR(VIU_OSD1_BLK2_CFG_W0)
#define P_VIU_OSD1_BLK3_CFG_W0 VPU_REG_ADDR(VIU_OSD1_BLK3_CFG_W0)
#define P_VIU_OSD1_BLK0_CFG_W1 VPU_REG_ADDR(VIU_OSD1_BLK0_CFG_W1)
#define P_VIU_OSD1_BLK1_CFG_W1 VPU_REG_ADDR(VIU_OSD1_BLK1_CFG_W1)
#define P_VIU_OSD1_BLK2_CFG_W1 VPU_REG_ADDR(VIU_OSD1_BLK2_CFG_W1)
#define P_VIU_OSD1_BLK3_CFG_W1 VPU_REG_ADDR(VIU_OSD1_BLK3_CFG_W1)
#define P_VIU_OSD1_BLK0_CFG_W2 VPU_REG_ADDR(VIU_OSD1_BLK0_CFG_W2)
#define P_VIU_OSD1_BLK1_CFG_W2 VPU_REG_ADDR(VIU_OSD1_BLK1_CFG_W2)
#define P_VIU_OSD1_BLK2_CFG_W2 VPU_REG_ADDR(VIU_OSD1_BLK2_CFG_W2)
#define P_VIU_OSD1_BLK3_CFG_W2 VPU_REG_ADDR(VIU_OSD1_BLK3_CFG_W2)
#define P_VIU_OSD1_BLK0_CFG_W3 VPU_REG_ADDR(VIU_OSD1_BLK0_CFG_W3)
#define P_VIU_OSD1_BLK1_CFG_W3 VPU_REG_ADDR(VIU_OSD1_BLK1_CFG_W3)
#define P_VIU_OSD1_BLK2_CFG_W3 VPU_REG_ADDR(VIU_OSD1_BLK2_CFG_W3)
#define P_VIU_OSD1_BLK3_CFG_W3 VPU_REG_ADDR(VIU_OSD1_BLK3_CFG_W3)
#define P_VIU_OSD1_BLK0_CFG_W4 VPU_REG_ADDR(VIU_OSD1_BLK0_CFG_W4)
#define P_VIU_OSD1_BLK1_CFG_W4 VPU_REG_ADDR(VIU_OSD1_BLK1_CFG_W4)
#define P_VIU_OSD1_BLK2_CFG_W4 VPU_REG_ADDR(VIU_OSD1_BLK2_CFG_W4)
#define P_VIU_OSD1_BLK3_CFG_W4 VPU_REG_ADDR(VIU_OSD1_BLK3_CFG_W4)
#define P_VIU_OSD1_FIFO_CTRL_STAT VPU_REG_ADDR(VIU_OSD1_FIFO_CTRL_STAT)
#define P_VIU_OSD1_TEST_RDDATA VPU_REG_ADDR(VIU_OSD1_TEST_RDDATA)
#define P_VIU_OSD1_PROT_CTRL VPU_REG_ADDR(VIU_OSD1_PROT_CTRL)
#define P_VIU_OSD2_CTRL_STAT VPU_REG_ADDR(VIU_OSD2_CTRL_STAT)
#define P_VIU_OSD2_CTRL_STAT2 VPU_REG_ADDR(VIU_OSD2_CTRL_STAT2)
#define P_VIU_OSD2_COLOR_ADDR VPU_REG_ADDR(VIU_OSD2_COLOR_ADDR)
#define P_VIU_OSD2_COLOR VPU_REG_ADDR(VIU_OSD2_COLOR)
#define P_VIU_OSD2_HL1_H_START_END VPU_REG_ADDR(VIU_OSD2_HL1_H_START_END)
#define P_VIU_OSD2_HL1_V_START_END VPU_REG_ADDR(VIU_OSD2_HL1_V_START_END)
#define P_VIU_OSD2_HL2_H_START_END VPU_REG_ADDR(VIU_OSD2_HL2_H_START_END)
#define P_VIU_OSD2_HL2_V_START_END VPU_REG_ADDR(VIU_OSD2_HL2_V_START_END)
#define P_VIU_OSD2_TCOLOR_AG0 VPU_REG_ADDR(VIU_OSD2_TCOLOR_AG0)
#define P_VIU_OSD2_TCOLOR_AG1 VPU_REG_ADDR(VIU_OSD2_TCOLOR_AG1)
#define P_VIU_OSD2_TCOLOR_AG2 VPU_REG_ADDR(VIU_OSD2_TCOLOR_AG2)
#define P_VIU_OSD2_TCOLOR_AG3 VPU_REG_ADDR(VIU_OSD2_TCOLOR_AG3)
#define P_VIU_OSD2_BLK0_CFG_W0 VPU_REG_ADDR(VIU_OSD2_BLK0_CFG_W0)
#define P_VIU_OSD2_BLK1_CFG_W0 VPU_REG_ADDR(VIU_OSD2_BLK1_CFG_W0)
#define P_VIU_OSD2_BLK2_CFG_W0 VPU_REG_ADDR(VIU_OSD2_BLK2_CFG_W0)
#define P_VIU_OSD2_BLK3_CFG_W0 VPU_REG_ADDR(VIU_OSD2_BLK3_CFG_W0)
#define P_VIU_OSD2_BLK0_CFG_W1 VPU_REG_ADDR(VIU_OSD2_BLK0_CFG_W1)
#define P_VIU_OSD2_BLK1_CFG_W1 VPU_REG_ADDR(VIU_OSD2_BLK1_CFG_W1)
#define P_VIU_OSD2_BLK2_CFG_W1 VPU_REG_ADDR(VIU_OSD2_BLK2_CFG_W1)
#define P_VIU_OSD2_BLK3_CFG_W1 VPU_REG_ADDR(VIU_OSD2_BLK3_CFG_W1)
#define P_VIU_OSD2_BLK0_CFG_W2 VPU_REG_ADDR(VIU_OSD2_BLK0_CFG_W2)
#define P_VIU_OSD2_BLK1_CFG_W2 VPU_REG_ADDR(VIU_OSD2_BLK1_CFG_W2)
#define P_VIU_OSD2_BLK2_CFG_W2 VPU_REG_ADDR(VIU_OSD2_BLK2_CFG_W2)
#define P_VIU_OSD2_BLK3_CFG_W2 VPU_REG_ADDR(VIU_OSD2_BLK3_CFG_W2)
#define P_VIU_OSD2_BLK0_CFG_W3 VPU_REG_ADDR(VIU_OSD2_BLK0_CFG_W3)
#define P_VIU_OSD2_BLK1_CFG_W3 VPU_REG_ADDR(VIU_OSD2_BLK1_CFG_W3)
#define P_VIU_OSD2_BLK2_CFG_W3 VPU_REG_ADDR(VIU_OSD2_BLK2_CFG_W3)
#define P_VIU_OSD2_BLK3_CFG_W3 VPU_REG_ADDR(VIU_OSD2_BLK3_CFG_W3)
#define P_VIU_OSD2_BLK0_CFG_W4 VPU_REG_ADDR(VIU_OSD2_BLK0_CFG_W4)
#define P_VIU_OSD2_BLK1_CFG_W4 VPU_REG_ADDR(VIU_OSD2_BLK1_CFG_W4)
#define P_VIU_OSD2_BLK2_CFG_W4 VPU_REG_ADDR(VIU_OSD2_BLK2_CFG_W4)
#define P_VIU_OSD2_BLK3_CFG_W4 VPU_REG_ADDR(VIU_OSD2_BLK3_CFG_W4)
#define P_VIU_OSD2_FIFO_CTRL_STAT VPU_REG_ADDR(VIU_OSD2_FIFO_CTRL_STAT)
#define P_VIU_OSD2_TEST_RDDATA VPU_REG_ADDR(VIU_OSD2_TEST_RDDATA)
#define P_VIU_OSD2_PROT_CTRL VPU_REG_ADDR(VIU_OSD2_PROT_CTRL)
#define P_VD1_IF0_GEN_REG VPU_REG_ADDR(VD1_IF0_GEN_REG)
#define P_VD1_IF0_CANVAS0 VPU_REG_ADDR(VD1_IF0_CANVAS0)
#define P_VD1_IF0_CANVAS1 VPU_REG_ADDR(VD1_IF0_CANVAS1)
#define P_VD1_IF0_LUMA_X0 VPU_REG_ADDR(VD1_IF0_LUMA_X0)
#define P_VD1_IF0_LUMA_Y0 VPU_REG_ADDR(VD1_IF0_LUMA_Y0)
#define P_VD1_IF0_CHROMA_X0 VPU_REG_ADDR(VD1_IF0_CHROMA_X0)
#define P_VD1_IF0_CHROMA_Y0 VPU_REG_ADDR(VD1_IF0_CHROMA_Y0)
#define P_VD1_IF0_LUMA_X1 VPU_REG_ADDR(VD1_IF0_LUMA_X1)
#define P_VD1_IF0_LUMA_Y1 VPU_REG_ADDR(VD1_IF0_LUMA_Y1)
#define P_VD1_IF0_CHROMA_X1 VPU_REG_ADDR(VD1_IF0_CHROMA_X1)
#define P_VD1_IF0_CHROMA_Y1 VPU_REG_ADDR(VD1_IF0_CHROMA_Y1)
#define P_VD1_IF0_RPT_LOOP VPU_REG_ADDR(VD1_IF0_RPT_LOOP)
#define P_VD1_IF0_LUMA0_RPT_PAT VPU_REG_ADDR(VD1_IF0_LUMA0_RPT_PAT)
#define P_VD1_IF0_CHROMA0_RPT_PAT VPU_REG_ADDR(VD1_IF0_CHROMA0_RPT_PAT)
#define P_VD1_IF0_LUMA1_RPT_PAT VPU_REG_ADDR(VD1_IF0_LUMA1_RPT_PAT)
#define P_VD1_IF0_CHROMA1_RPT_PAT VPU_REG_ADDR(VD1_IF0_CHROMA1_RPT_PAT)
#define P_VD1_IF0_LUMA_PSEL VPU_REG_ADDR(VD1_IF0_LUMA_PSEL)
#define P_VD1_IF0_CHROMA_PSEL VPU_REG_ADDR(VD1_IF0_CHROMA_PSEL)
#define P_VD1_IF0_DUMMY_PIXEL VPU_REG_ADDR(VD1_IF0_DUMMY_PIXEL)
#define P_VD1_IF0_LUMA_FIFO_SIZE VPU_REG_ADDR(VD1_IF0_LUMA_FIFO_SIZE)
#define P_VD1_IF0_RANGE_MAP_Y VPU_REG_ADDR(VD1_IF0_RANGE_MAP_Y)
#define P_VD1_IF0_RANGE_MAP_CB VPU_REG_ADDR(VD1_IF0_RANGE_MAP_CB)
#define P_VD1_IF0_RANGE_MAP_CR VPU_REG_ADDR(VD1_IF0_RANGE_MAP_CR)
#define P_VD1_IF0_GEN_REG2 VPU_REG_ADDR(VD1_IF0_GEN_REG2)
#define P_VD1_IF0_PROT_CNTL VPU_REG_ADDR(VD1_IF0_PROT_CNTL)
#define P_VIU_VD1_FMT_CTRL VPU_REG_ADDR(VIU_VD1_FMT_CTRL)
#define P_VIU_VD1_FMT_W VPU_REG_ADDR(VIU_VD1_FMT_W)
#define P_VD2_IF0_GEN_REG VPU_REG_ADDR(VD2_IF0_GEN_REG)
#define P_VD2_IF0_CANVAS0 VPU_REG_ADDR(VD2_IF0_CANVAS0)
#define P_VD2_IF0_CANVAS1 VPU_REG_ADDR(VD2_IF0_CANVAS1)
#define P_VD2_IF0_LUMA_X0 VPU_REG_ADDR(VD2_IF0_LUMA_X0)
#define P_VD2_IF0_LUMA_Y0 VPU_REG_ADDR(VD2_IF0_LUMA_Y0)
#define P_VD2_IF0_CHROMA_X0 VPU_REG_ADDR(VD2_IF0_CHROMA_X0)
#define P_VD2_IF0_CHROMA_Y0 VPU_REG_ADDR(VD2_IF0_CHROMA_Y0)
#define P_VD2_IF0_LUMA_X1 VPU_REG_ADDR(VD2_IF0_LUMA_X1)
#define P_VD2_IF0_LUMA_Y1 VPU_REG_ADDR(VD2_IF0_LUMA_Y1)
#define P_VD2_IF0_CHROMA_X1 VPU_REG_ADDR(VD2_IF0_CHROMA_X1)
#define P_VD2_IF0_CHROMA_Y1 VPU_REG_ADDR(VD2_IF0_CHROMA_Y1)
#define P_VD2_IF0_RPT_LOOP VPU_REG_ADDR(VD2_IF0_RPT_LOOP)
#define P_VD2_IF0_LUMA0_RPT_PAT VPU_REG_ADDR(VD2_IF0_LUMA0_RPT_PAT)
#define P_VD2_IF0_CHROMA0_RPT_PAT VPU_REG_ADDR(VD2_IF0_CHROMA0_RPT_PAT)
#define P_VD2_IF0_LUMA1_RPT_PAT VPU_REG_ADDR(VD2_IF0_LUMA1_RPT_PAT)
#define P_VD2_IF0_CHROMA1_RPT_PAT VPU_REG_ADDR(VD2_IF0_CHROMA1_RPT_PAT)
#define P_VD2_IF0_LUMA_PSEL VPU_REG_ADDR(VD2_IF0_LUMA_PSEL)
#define P_VD2_IF0_CHROMA_PSEL VPU_REG_ADDR(VD2_IF0_CHROMA_PSEL)
#define P_VD2_IF0_DUMMY_PIXEL VPU_REG_ADDR(VD2_IF0_DUMMY_PIXEL)
#define P_VD2_IF0_LUMA_FIFO_SIZE VPU_REG_ADDR(VD2_IF0_LUMA_FIFO_SIZE)
#define P_VD2_IF0_RANGE_MAP_Y VPU_REG_ADDR(VD2_IF0_RANGE_MAP_Y)
#define P_VD2_IF0_RANGE_MAP_CB VPU_REG_ADDR(VD2_IF0_RANGE_MAP_CB)
#define P_VD2_IF0_RANGE_MAP_CR VPU_REG_ADDR(VD2_IF0_RANGE_MAP_CR)
#define P_VD2_IF0_GEN_REG2 VPU_REG_ADDR(VD2_IF0_GEN_REG2)
#define P_VD2_IF0_PROT_CNTL VPU_REG_ADDR(VD2_IF0_PROT_CNTL)
#define P_VIU_VD2_FMT_CTRL VPU_REG_ADDR(VIU_VD2_FMT_CTRL)
#define P_VIU_VD2_FMT_W VPU_REG_ADDR(VIU_VD2_FMT_W)
#define P_LDIM_STTS_GCLK_CTRL0 VPU_REG_ADDR(LDIM_STTS_GCLK_CTRL0)
#define P_LDIM_STTS_CTRL0 VPU_REG_ADDR(LDIM_STTS_CTRL0)
#define P_LDIM_STTS_WIDTHM1_HEIGHTM1 VPU_REG_ADDR(LDIM_STTS_WIDTHM1_HEIGHTM1)
#define P_LDIM_STTS_MATRIX_COEF00_01 VPU_REG_ADDR(LDIM_STTS_MATRIX_COEF00_01)
#define P_LDIM_STTS_MATRIX_COEF02_10 VPU_REG_ADDR(LDIM_STTS_MATRIX_COEF02_10)
#define P_LDIM_STTS_MATRIX_COEF11_12 VPU_REG_ADDR(LDIM_STTS_MATRIX_COEF11_12)
#define P_LDIM_STTS_MATRIX_COEF20_21 VPU_REG_ADDR(LDIM_STTS_MATRIX_COEF20_21)
#define P_LDIM_STTS_MATRIX_COEF22 VPU_REG_ADDR(LDIM_STTS_MATRIX_COEF22)
#define P_LDIM_STTS_MATRIX_OFFSET0_1 VPU_REG_ADDR(LDIM_STTS_MATRIX_OFFSET0_1)
#define P_LDIM_STTS_MATRIX_OFFSET2 VPU_REG_ADDR(LDIM_STTS_MATRIX_OFFSET2)
#define P_LDIM_STTS_MATRIX_PRE_OFFSET0_1 VPU_REG_ADDR(LDIM_STTS_MATRIX_PRE_OFFSET0_1)
#define P_LDIM_STTS_MATRIX_PRE_OFFSET2 VPU_REG_ADDR(LDIM_STTS_MATRIX_PRE_OFFSET2)
#define P_LDIM_STTS_MATRIX_HL_COLOR VPU_REG_ADDR(LDIM_STTS_MATRIX_HL_COLOR)
#define P_LDIM_STTS_MATRIX_PROBE_POS VPU_REG_ADDR(LDIM_STTS_MATRIX_PROBE_POS)
#define P_LDIM_STTS_MATRIX_PROBE_COLOR VPU_REG_ADDR(LDIM_STTS_MATRIX_PROBE_COLOR)
#define P_LDIM_STTS_HIST_REGION_IDX VPU_REG_ADDR(LDIM_STTS_HIST_REGION_IDX)
#define P_LDIM_STTS_HIST_SET_REGION VPU_REG_ADDR(LDIM_STTS_HIST_SET_REGION)
#define P_LDIM_STTS_HIST_READ_REGION VPU_REG_ADDR(LDIM_STTS_HIST_READ_REGION)
#define P_DI_PRE_CTRL VPU_REG_ADDR(DI_PRE_CTRL)
#define P_DI_POST_CTRL VPU_REG_ADDR(DI_POST_CTRL)
#define P_DI_POST_SIZE VPU_REG_ADDR(DI_POST_SIZE)
#define P_DI_PRE_SIZE VPU_REG_ADDR(DI_PRE_SIZE)
#define P_DI_EI_CTRL0 VPU_REG_ADDR(DI_EI_CTRL0)
#define P_DI_EI_CTRL1 VPU_REG_ADDR(DI_EI_CTRL1)
#define P_DI_EI_CTRL2 VPU_REG_ADDR(DI_EI_CTRL2)
#define P_DI_NR_CTRL0 VPU_REG_ADDR(DI_NR_CTRL0)
#define P_DI_NR_CTRL1 VPU_REG_ADDR(DI_NR_CTRL1)
#define P_DI_NR_CTRL2 VPU_REG_ADDR(DI_NR_CTRL2)
#define P_DI_NR_CTRL3 VPU_REG_ADDR(DI_NR_CTRL3)
#define P_DI_MTN_CTRL VPU_REG_ADDR(DI_MTN_CTRL)
#define P_DI_MTN_CTRL1 VPU_REG_ADDR(DI_MTN_CTRL1)
#define P_DI_BLEND_CTRL VPU_REG_ADDR(DI_BLEND_CTRL)
#define P_DI_BLEND_CTRL1 VPU_REG_ADDR(DI_BLEND_CTRL1)
#define P_DI_BLEND_CTRL2 VPU_REG_ADDR(DI_BLEND_CTRL2)
#define P_DI_BLEND_REG0_X VPU_REG_ADDR(DI_BLEND_REG0_X)
#define P_DI_BLEND_REG0_Y VPU_REG_ADDR(DI_BLEND_REG0_Y)
#define P_DI_BLEND_REG1_X VPU_REG_ADDR(DI_BLEND_REG1_X)
#define P_DI_BLEND_REG1_Y VPU_REG_ADDR(DI_BLEND_REG1_Y)
#define P_DI_BLEND_REG2_X VPU_REG_ADDR(DI_BLEND_REG2_X)
#define P_DI_BLEND_REG2_Y VPU_REG_ADDR(DI_BLEND_REG2_Y)
#define P_DI_BLEND_REG3_X VPU_REG_ADDR(DI_BLEND_REG3_X)
#define P_DI_BLEND_REG3_Y VPU_REG_ADDR(DI_BLEND_REG3_Y)
#define P_DI_CLKG_CTRL VPU_REG_ADDR(DI_CLKG_CTRL)
#define P_DI_EI_CTRL3 VPU_REG_ADDR(DI_EI_CTRL3)
#define P_DI_EI_CTRL4 VPU_REG_ADDR(DI_EI_CTRL4)
#define P_DI_EI_CTRL5 VPU_REG_ADDR(DI_EI_CTRL5)
#define P_DI_EI_CTRL6 VPU_REG_ADDR(DI_EI_CTRL6)
#define P_DI_EI_CTRL7 VPU_REG_ADDR(DI_EI_CTRL7)
#define P_DI_EI_CTRL8 VPU_REG_ADDR(DI_EI_CTRL8)
#define P_DI_EI_CTRL9 VPU_REG_ADDR(DI_EI_CTRL9)
#define P_DI_EI_CTRL10 VPU_REG_ADDR(DI_EI_CTRL10)
#define P_DI_EI_CTRL11 VPU_REG_ADDR(DI_EI_CTRL11)
#define P_DI_EI_CTRL12 VPU_REG_ADDR(DI_EI_CTRL12)
#define P_DI_EI_CTRL13 VPU_REG_ADDR(DI_EI_CTRL13)
#define P_DI_EI_XWIN0 VPU_REG_ADDR(DI_EI_XWIN0)
#define P_DI_EI_XWIN1 VPU_REG_ADDR(DI_EI_XWIN1)
#define P_DI_MC_REG0_X VPU_REG_ADDR(DI_MC_REG0_X)
#define P_DI_MC_REG0_Y VPU_REG_ADDR(DI_MC_REG0_Y)
#define P_DI_MC_REG1_X VPU_REG_ADDR(DI_MC_REG1_X)
#define P_DI_MC_REG1_Y VPU_REG_ADDR(DI_MC_REG1_Y)
#define P_DI_MC_REG2_X VPU_REG_ADDR(DI_MC_REG2_X)
#define P_DI_MC_REG2_Y VPU_REG_ADDR(DI_MC_REG2_Y)
#define P_DI_MC_REG3_X VPU_REG_ADDR(DI_MC_REG3_X)
#define P_DI_MC_REG3_Y VPU_REG_ADDR(DI_MC_REG3_Y)
#define P_DI_MC_REG4_X VPU_REG_ADDR(DI_MC_REG4_X)
#define P_DI_MC_REG4_Y VPU_REG_ADDR(DI_MC_REG4_Y)
#define P_DI_MC_32LVL0 VPU_REG_ADDR(DI_MC_32LVL0)
#define P_DI_MC_32LVL1 VPU_REG_ADDR(DI_MC_32LVL1)
#define P_DI_MC_22LVL0 VPU_REG_ADDR(DI_MC_22LVL0)
#define P_DI_MC_22LVL1 VPU_REG_ADDR(DI_MC_22LVL1)
#define P_DI_MC_22LVL2 VPU_REG_ADDR(DI_MC_22LVL2)
#define P_DI_MC_CTRL VPU_REG_ADDR(DI_MC_CTRL)
#define P_DI_INTR_CTRL VPU_REG_ADDR(DI_INTR_CTRL)
#define P_DI_INFO_ADDR VPU_REG_ADDR(DI_INFO_ADDR)
#define P_DI_INFO_DATA VPU_REG_ADDR(DI_INFO_DATA)
#define P_DI_PRE_HOLD VPU_REG_ADDR(DI_PRE_HOLD)
#define P_DI_MTN_1_CTRL1 VPU_REG_ADDR(DI_MTN_1_CTRL1)
#define P_DI_MTN_1_CTRL2 VPU_REG_ADDR(DI_MTN_1_CTRL2)
#define P_DI_MTN_1_CTRL3 VPU_REG_ADDR(DI_MTN_1_CTRL3)
#define P_DI_MTN_1_CTRL4 VPU_REG_ADDR(DI_MTN_1_CTRL4)
#define P_DI_MTN_1_CTRL5 VPU_REG_ADDR(DI_MTN_1_CTRL5)
#define P_DI_MTN_1_CTRL6 VPU_REG_ADDR(DI_MTN_1_CTRL6)
#define P_DI_MTN_1_CTRL7 VPU_REG_ADDR(DI_MTN_1_CTRL7)
#define P_DI_MTN_1_CTRL8 VPU_REG_ADDR(DI_MTN_1_CTRL8)
#define P_DI_MTN_1_CTRL9 VPU_REG_ADDR(DI_MTN_1_CTRL9)
#define P_DI_MTN_1_CTRL10 VPU_REG_ADDR(DI_MTN_1_CTRL10)
#define P_DI_MTN_1_CTRL11 VPU_REG_ADDR(DI_MTN_1_CTRL11)
#define P_DI_MTN_1_CTRL12 VPU_REG_ADDR(DI_MTN_1_CTRL12)
#define P_DET3D_MOTN_CFG VPU_REG_ADDR(DET3D_MOTN_CFG)
#define P_DET3D_CB_CFG VPU_REG_ADDR(DET3D_CB_CFG)
#define P_DET3D_SPLT_CFG VPU_REG_ADDR(DET3D_SPLT_CFG)
#define P_DET3D_HV_MUTE VPU_REG_ADDR(DET3D_HV_MUTE)
#define P_DET3D_MAT_STA_P1M1 VPU_REG_ADDR(DET3D_MAT_STA_P1M1)
#define P_DET3D_MAT_STA_P1TH VPU_REG_ADDR(DET3D_MAT_STA_P1TH)
#define P_DET3D_MAT_STA_M1TH VPU_REG_ADDR(DET3D_MAT_STA_M1TH)
#define P_DET3D_MAT_STA_RSFT VPU_REG_ADDR(DET3D_MAT_STA_RSFT)
#define P_DET3D_MAT_SYMTC_TH VPU_REG_ADDR(DET3D_MAT_SYMTC_TH)
#define P_DET3D_RO_DET_CB_HOR VPU_REG_ADDR(DET3D_RO_DET_CB_HOR)
#define P_DET3D_RO_DET_CB_VER VPU_REG_ADDR(DET3D_RO_DET_CB_VER)
#define P_DET3D_RO_SPLT_HT VPU_REG_ADDR(DET3D_RO_SPLT_HT)
#define P_NR2_MET_NM_CTRL VPU_REG_ADDR(NR2_MET_NM_CTRL)
#define P_NR2_MET_NM_YCTRL VPU_REG_ADDR(NR2_MET_NM_YCTRL)
#define P_NR2_MET_NM_CCTRL VPU_REG_ADDR(NR2_MET_NM_CCTRL)
#define P_NR2_MET_NM_TNR VPU_REG_ADDR(NR2_MET_NM_TNR)
#define P_NR2_MET_NMFRM_TNR_YLEV VPU_REG_ADDR(NR2_MET_NMFRM_TNR_YLEV)
#define P_NR2_MET_NMFRM_TNR_YCNT VPU_REG_ADDR(NR2_MET_NMFRM_TNR_YCNT)
#define P_NR2_MET_NMFRM_TNR_CLEV VPU_REG_ADDR(NR2_MET_NMFRM_TNR_CLEV)
#define P_NR2_MET_NMFRM_TNR_CCNT VPU_REG_ADDR(NR2_MET_NMFRM_TNR_CCNT)
#define P_NR2_3DEN_MODE VPU_REG_ADDR(NR2_3DEN_MODE)
#define P_NR2_IIR_CTRL VPU_REG_ADDR(NR2_IIR_CTRL)
#define P_NR2_SW_EN VPU_REG_ADDR(NR2_SW_EN)
#define P_NR2_FRM_SIZE VPU_REG_ADDR(NR2_FRM_SIZE)
#define P_NR2_SNR_SAD_CFG VPU_REG_ADDR(NR2_SNR_SAD_CFG)
#define P_NR2_MATNR_SNR_OS VPU_REG_ADDR(NR2_MATNR_SNR_OS)
#define P_NR2_MATNR_SNR_NRM_CFG VPU_REG_ADDR(NR2_MATNR_SNR_NRM_CFG)
#define P_NR2_MATNR_SNR_NRM_GAIN VPU_REG_ADDR(NR2_MATNR_SNR_NRM_GAIN)
#define P_NR2_MATNR_SNR_LPF_CFG VPU_REG_ADDR(NR2_MATNR_SNR_LPF_CFG)
#define P_NR2_MATNR_SNR_USF_GAIN VPU_REG_ADDR(NR2_MATNR_SNR_USF_GAIN)
#define P_NR2_MATNR_SNR_EDGE2B VPU_REG_ADDR(NR2_MATNR_SNR_EDGE2B)
#define P_NR2_MATNR_BETA_EGAIN VPU_REG_ADDR(NR2_MATNR_BETA_EGAIN)
#define P_NR2_MATNR_BETA_BRT VPU_REG_ADDR(NR2_MATNR_BETA_BRT)
#define P_NR2_MATNR_XBETA_CFG VPU_REG_ADDR(NR2_MATNR_XBETA_CFG)
#define P_NR2_MATNR_YBETA_SCL VPU_REG_ADDR(NR2_MATNR_YBETA_SCL)
#define P_NR2_MATNR_CBETA_SCL VPU_REG_ADDR(NR2_MATNR_CBETA_SCL)
#define P_NR2_SNR_MASK VPU_REG_ADDR(NR2_SNR_MASK)
#define P_NR2_SAD2NORM_LUT0 VPU_REG_ADDR(NR2_SAD2NORM_LUT0)
#define P_NR2_SAD2NORM_LUT1 VPU_REG_ADDR(NR2_SAD2NORM_LUT1)
#define P_NR2_SAD2NORM_LUT2 VPU_REG_ADDR(NR2_SAD2NORM_LUT2)
#define P_NR2_SAD2NORM_LUT3 VPU_REG_ADDR(NR2_SAD2NORM_LUT3)
#define P_NR2_EDGE2BETA_LUT0 VPU_REG_ADDR(NR2_EDGE2BETA_LUT0)
#define P_NR2_EDGE2BETA_LUT1 VPU_REG_ADDR(NR2_EDGE2BETA_LUT1)
#define P_NR2_EDGE2BETA_LUT2 VPU_REG_ADDR(NR2_EDGE2BETA_LUT2)
#define P_NR2_EDGE2BETA_LUT3 VPU_REG_ADDR(NR2_EDGE2BETA_LUT3)
#define P_NR2_MOTION2BETA_LUT0 VPU_REG_ADDR(NR2_MOTION2BETA_LUT0)
#define P_NR2_MOTION2BETA_LUT1 VPU_REG_ADDR(NR2_MOTION2BETA_LUT1)
#define P_NR2_MOTION2BETA_LUT2 VPU_REG_ADDR(NR2_MOTION2BETA_LUT2)
#define P_NR2_MOTION2BETA_LUT3 VPU_REG_ADDR(NR2_MOTION2BETA_LUT3)
#define P_NR2_MATNR_MTN_CRTL VPU_REG_ADDR(NR2_MATNR_MTN_CRTL)
#define P_NR2_MATNR_MTN_CRTL2 VPU_REG_ADDR(NR2_MATNR_MTN_CRTL2)
#define P_NR2_MATNR_MTN_COR VPU_REG_ADDR(NR2_MATNR_MTN_COR)
#define P_NR2_MATNR_MTN_GAIN VPU_REG_ADDR(NR2_MATNR_MTN_GAIN)
#define P_NR2_MATNR_DEGHOST VPU_REG_ADDR(NR2_MATNR_DEGHOST)
#define P_NR2_MATNR_ALPHALP_LUT0 VPU_REG_ADDR(NR2_MATNR_ALPHALP_LUT0)
#define P_NR2_MATNR_ALPHALP_LUT1 VPU_REG_ADDR(NR2_MATNR_ALPHALP_LUT1)
#define P_NR2_MATNR_ALPHALP_LUT2 VPU_REG_ADDR(NR2_MATNR_ALPHALP_LUT2)
#define P_NR2_MATNR_ALPHALP_LUT3 VPU_REG_ADDR(NR2_MATNR_ALPHALP_LUT3)
#define P_NR2_MATNR_ALPHAHP_LUT0 VPU_REG_ADDR(NR2_MATNR_ALPHAHP_LUT0)
#define P_NR2_MATNR_ALPHAHP_LUT1 VPU_REG_ADDR(NR2_MATNR_ALPHAHP_LUT1)
#define P_NR2_MATNR_ALPHAHP_LUT2 VPU_REG_ADDR(NR2_MATNR_ALPHAHP_LUT2)
#define P_NR2_MATNR_ALPHAHP_LUT3 VPU_REG_ADDR(NR2_MATNR_ALPHAHP_LUT3)
#define P_NR2_MATNR_MTNB_BRT VPU_REG_ADDR(NR2_MATNR_MTNB_BRT)
#define P_NR2_CUE_MODE VPU_REG_ADDR(NR2_CUE_MODE)
#define P_NR2_CUE_CON_MOT_TH VPU_REG_ADDR(NR2_CUE_CON_MOT_TH)
#define P_NR2_CUE_CON_DIF0 VPU_REG_ADDR(NR2_CUE_CON_DIF0)
#define P_NR2_CUE_CON_DIF1 VPU_REG_ADDR(NR2_CUE_CON_DIF1)
#define P_NR2_CUE_CON_DIF2 VPU_REG_ADDR(NR2_CUE_CON_DIF2)
#define P_NR2_CUE_CON_DIF3 VPU_REG_ADDR(NR2_CUE_CON_DIF3)
#define P_NR2_CUE_PRG_DIF VPU_REG_ADDR(NR2_CUE_PRG_DIF)
#define P_NR2_CONV_MODE VPU_REG_ADDR(NR2_CONV_MODE)
#define P_DET3D_RO_SPLT_HB VPU_REG_ADDR(DET3D_RO_SPLT_HB)
#define P_DET3D_RO_SPLT_VL VPU_REG_ADDR(DET3D_RO_SPLT_VL)
#define P_DET3D_RO_SPLT_VR VPU_REG_ADDR(DET3D_RO_SPLT_VR)
#define P_DET3D_RO_MAT_LUMA_LR VPU_REG_ADDR(DET3D_RO_MAT_LUMA_LR)
#define P_DET3D_RO_MAT_LUMA_TB VPU_REG_ADDR(DET3D_RO_MAT_LUMA_TB)
#define P_DET3D_RO_MAT_CHRU_LR VPU_REG_ADDR(DET3D_RO_MAT_CHRU_LR)
#define P_DET3D_RO_MAT_CHRU_TB VPU_REG_ADDR(DET3D_RO_MAT_CHRU_TB)
#define P_DET3D_RO_MAT_CHRV_LR VPU_REG_ADDR(DET3D_RO_MAT_CHRV_LR)
#define P_DET3D_RO_MAT_CHRV_TB VPU_REG_ADDR(DET3D_RO_MAT_CHRV_TB)
#define P_DET3D_RO_MAT_HEDG_LR VPU_REG_ADDR(DET3D_RO_MAT_HEDG_LR)
#define P_DET3D_RO_MAT_HEDG_TB VPU_REG_ADDR(DET3D_RO_MAT_HEDG_TB)
#define P_DET3D_RO_MAT_VEDG_LR VPU_REG_ADDR(DET3D_RO_MAT_VEDG_LR)
#define P_DET3D_RO_MAT_VEDG_TB VPU_REG_ADDR(DET3D_RO_MAT_VEDG_TB)
#define P_DET3D_RO_MAT_MOTN_LR VPU_REG_ADDR(DET3D_RO_MAT_MOTN_LR)
#define P_DET3D_RO_MAT_MOTN_TB VPU_REG_ADDR(DET3D_RO_MAT_MOTN_TB)
#define P_DET3D_RO_FRM_MOTN VPU_REG_ADDR(DET3D_RO_FRM_MOTN)
#define P_DET3D_RAMRD_ADDR_PORT VPU_REG_ADDR(DET3D_RAMRD_ADDR_PORT)
#define P_DET3D_RAMRD_DATA_PORT VPU_REG_ADDR(DET3D_RAMRD_DATA_PORT)
#define P_NR2_CFR_PARA_CFG0 VPU_REG_ADDR(NR2_CFR_PARA_CFG0)
#define P_NR2_CFR_PARA_CFG1 VPU_REG_ADDR(NR2_CFR_PARA_CFG1)
#define P_DI_NR_1_CTRL0 VPU_REG_ADDR(DI_NR_1_CTRL0)
#define P_DI_NR_1_CTRL1 VPU_REG_ADDR(DI_NR_1_CTRL1)
#define P_DI_NR_1_CTRL2 VPU_REG_ADDR(DI_NR_1_CTRL2)
#define P_DI_NR_1_CTRL3 VPU_REG_ADDR(DI_NR_1_CTRL3)
#define P_DI_CONTWR_X VPU_REG_ADDR(DI_CONTWR_X)
#define P_DI_CONTWR_Y VPU_REG_ADDR(DI_CONTWR_Y)
#define P_DI_CONTWR_CTRL VPU_REG_ADDR(DI_CONTWR_CTRL)
#define P_DI_CONTPRD_X VPU_REG_ADDR(DI_CONTPRD_X)
#define P_DI_CONTPRD_Y VPU_REG_ADDR(DI_CONTPRD_Y)
#define P_DI_CONTP2RD_X VPU_REG_ADDR(DI_CONTP2RD_X)
#define P_DI_CONTP2RD_Y VPU_REG_ADDR(DI_CONTP2RD_Y)
#define P_DI_CONTRD_CTRL VPU_REG_ADDR(DI_CONTRD_CTRL)
#define P_DI_NRWR_X VPU_REG_ADDR(DI_NRWR_X)
#define P_DI_NRWR_Y VPU_REG_ADDR(DI_NRWR_Y)
#define P_DI_NRWR_CTRL VPU_REG_ADDR(DI_NRWR_CTRL)
#define P_DI_MTNWR_X VPU_REG_ADDR(DI_MTNWR_X)
#define P_DI_MTNWR_Y VPU_REG_ADDR(DI_MTNWR_Y)
#define P_DI_MTNWR_CTRL VPU_REG_ADDR(DI_MTNWR_CTRL)
#define P_DI_DIWR_X VPU_REG_ADDR(DI_DIWR_X)
#define P_DI_DIWR_Y VPU_REG_ADDR(DI_DIWR_Y)
#define P_DI_DIWR_CTRL VPU_REG_ADDR(DI_DIWR_CTRL)
#define P_DI_MTNCRD_X VPU_REG_ADDR(DI_MTNCRD_X)
#define P_DI_MTNCRD_Y VPU_REG_ADDR(DI_MTNCRD_Y)
#define P_DI_MTNPRD_X VPU_REG_ADDR(DI_MTNPRD_X)
#define P_DI_MTNPRD_Y VPU_REG_ADDR(DI_MTNPRD_Y)
#define P_DI_MTNRD_CTRL VPU_REG_ADDR(DI_MTNRD_CTRL)
#define P_DI_INP_GEN_REG VPU_REG_ADDR(DI_INP_GEN_REG)
#define P_DI_INP_CANVAS0 VPU_REG_ADDR(DI_INP_CANVAS0)
#define P_DI_INP_LUMA_X0 VPU_REG_ADDR(DI_INP_LUMA_X0)
#define P_DI_INP_LUMA_Y0 VPU_REG_ADDR(DI_INP_LUMA_Y0)
#define P_DI_INP_CHROMA_X0 VPU_REG_ADDR(DI_INP_CHROMA_X0)
#define P_DI_INP_CHROMA_Y0 VPU_REG_ADDR(DI_INP_CHROMA_Y0)
#define P_DI_INP_RPT_LOOP VPU_REG_ADDR(DI_INP_RPT_LOOP)
#define P_DI_INP_LUMA0_RPT_PAT VPU_REG_ADDR(DI_INP_LUMA0_RPT_PAT)
#define P_DI_INP_CHROMA0_RPT_PAT VPU_REG_ADDR(DI_INP_CHROMA0_RPT_PAT)
#define P_DI_INP_DUMMY_PIXEL VPU_REG_ADDR(DI_INP_DUMMY_PIXEL)
#define P_DI_INP_LUMA_FIFO_SIZE VPU_REG_ADDR(DI_INP_LUMA_FIFO_SIZE)
#define P_DI_INP_RANGE_MAP_Y VPU_REG_ADDR(DI_INP_RANGE_MAP_Y)
#define P_DI_INP_RANGE_MAP_CB VPU_REG_ADDR(DI_INP_RANGE_MAP_CB)
#define P_DI_INP_RANGE_MAP_CR VPU_REG_ADDR(DI_INP_RANGE_MAP_CR)
#define P_DI_INP_GEN_REG2 VPU_REG_ADDR(DI_INP_GEN_REG2)
#define P_DI_INP_FMT_CTRL VPU_REG_ADDR(DI_INP_FMT_CTRL)
#define P_DI_INP_FMT_W VPU_REG_ADDR(DI_INP_FMT_W)
#define P_DI_MEM_GEN_REG VPU_REG_ADDR(DI_MEM_GEN_REG)
#define P_DI_MEM_CANVAS0 VPU_REG_ADDR(DI_MEM_CANVAS0)
#define P_DI_MEM_LUMA_X0 VPU_REG_ADDR(DI_MEM_LUMA_X0)
#define P_DI_MEM_LUMA_Y0 VPU_REG_ADDR(DI_MEM_LUMA_Y0)
#define P_DI_MEM_CHROMA_X0 VPU_REG_ADDR(DI_MEM_CHROMA_X0)
#define P_DI_MEM_CHROMA_Y0 VPU_REG_ADDR(DI_MEM_CHROMA_Y0)
#define P_DI_MEM_RPT_LOOP VPU_REG_ADDR(DI_MEM_RPT_LOOP)
#define P_DI_MEM_LUMA0_RPT_PAT VPU_REG_ADDR(DI_MEM_LUMA0_RPT_PAT)
#define P_DI_MEM_CHROMA0_RPT_PAT VPU_REG_ADDR(DI_MEM_CHROMA0_RPT_PAT)
#define P_DI_MEM_DUMMY_PIXEL VPU_REG_ADDR(DI_MEM_DUMMY_PIXEL)
#define P_DI_MEM_LUMA_FIFO_SIZE VPU_REG_ADDR(DI_MEM_LUMA_FIFO_SIZE)
#define P_DI_MEM_RANGE_MAP_Y VPU_REG_ADDR(DI_MEM_RANGE_MAP_Y)
#define P_DI_MEM_RANGE_MAP_CB VPU_REG_ADDR(DI_MEM_RANGE_MAP_CB)
#define P_DI_MEM_RANGE_MAP_CR VPU_REG_ADDR(DI_MEM_RANGE_MAP_CR)
#define P_DI_MEM_GEN_REG2 VPU_REG_ADDR(DI_MEM_GEN_REG2)
#define P_DI_MEM_FMT_CTRL VPU_REG_ADDR(DI_MEM_FMT_CTRL)
#define P_DI_MEM_FMT_W VPU_REG_ADDR(DI_MEM_FMT_W)
#define P_DI_IF1_GEN_REG VPU_REG_ADDR(DI_IF1_GEN_REG)
#define P_DI_IF1_CANVAS0 VPU_REG_ADDR(DI_IF1_CANVAS0)
#define P_DI_IF1_LUMA_X0 VPU_REG_ADDR(DI_IF1_LUMA_X0)
#define P_DI_IF1_LUMA_Y0 VPU_REG_ADDR(DI_IF1_LUMA_Y0)
#define P_DI_IF1_CHROMA_X0 VPU_REG_ADDR(DI_IF1_CHROMA_X0)
#define P_DI_IF1_CHROMA_Y0 VPU_REG_ADDR(DI_IF1_CHROMA_Y0)
#define P_DI_IF1_RPT_LOOP VPU_REG_ADDR(DI_IF1_RPT_LOOP)
#define P_DI_IF1_LUMA0_RPT_PAT VPU_REG_ADDR(DI_IF1_LUMA0_RPT_PAT)
#define P_DI_IF1_CHROMA0_RPT_PAT VPU_REG_ADDR(DI_IF1_CHROMA0_RPT_PAT)
#define P_DI_IF1_DUMMY_PIXEL VPU_REG_ADDR(DI_IF1_DUMMY_PIXEL)
#define P_DI_IF1_LUMA_FIFO_SIZE VPU_REG_ADDR(DI_IF1_LUMA_FIFO_SIZE)
#define P_DI_IF1_RANGE_MAP_Y VPU_REG_ADDR(DI_IF1_RANGE_MAP_Y)
#define P_DI_IF1_RANGE_MAP_CB VPU_REG_ADDR(DI_IF1_RANGE_MAP_CB)
#define P_DI_IF1_RANGE_MAP_CR VPU_REG_ADDR(DI_IF1_RANGE_MAP_CR)
#define P_DI_IF1_GEN_REG2 VPU_REG_ADDR(DI_IF1_GEN_REG2)
#define P_DI_IF1_FMT_CTRL VPU_REG_ADDR(DI_IF1_FMT_CTRL)
#define P_DI_IF1_FMT_W VPU_REG_ADDR(DI_IF1_FMT_W)
#define P_DI_CHAN2_GEN_REG VPU_REG_ADDR(DI_CHAN2_GEN_REG)
#define P_DI_CHAN2_CANVAS0 VPU_REG_ADDR(DI_CHAN2_CANVAS0)
#define P_DI_CHAN2_LUMA_X0 VPU_REG_ADDR(DI_CHAN2_LUMA_X0)
#define P_DI_CHAN2_LUMA_Y0 VPU_REG_ADDR(DI_CHAN2_LUMA_Y0)
#define P_DI_CHAN2_CHROMA_X0 VPU_REG_ADDR(DI_CHAN2_CHROMA_X0)
#define P_DI_CHAN2_CHROMA_Y0 VPU_REG_ADDR(DI_CHAN2_CHROMA_Y0)
#define P_DI_CHAN2_RPT_LOOP VPU_REG_ADDR(DI_CHAN2_RPT_LOOP)
#define P_DI_CHAN2_LUMA0_RPT_PAT VPU_REG_ADDR(DI_CHAN2_LUMA0_RPT_PAT)
#define P_DI_CHAN2_CHROMA0_RPT_PAT VPU_REG_ADDR(DI_CHAN2_CHROMA0_RPT_PAT)
#define P_DI_CHAN2_DUMMY_PIXEL VPU_REG_ADDR(DI_CHAN2_DUMMY_PIXEL)
#define P_DI_CHAN2_LUMA_FIFO_SIZE VPU_REG_ADDR(DI_CHAN2_LUMA_FIFO_SIZE)
#define P_DI_CHAN2_RANGE_MAP_Y VPU_REG_ADDR(DI_CHAN2_RANGE_MAP_Y)
#define P_DI_CHAN2_RANGE_MAP_CB VPU_REG_ADDR(DI_CHAN2_RANGE_MAP_CB)
#define P_DI_CHAN2_RANGE_MAP_CR VPU_REG_ADDR(DI_CHAN2_RANGE_MAP_CR)
#define P_DI_CHAN2_GEN_REG2 VPU_REG_ADDR(DI_CHAN2_GEN_REG2)
#define P_DI_CHAN2_FMT_CTRL VPU_REG_ADDR(DI_CHAN2_FMT_CTRL)
#define P_DI_CHAN2_FMT_W VPU_REG_ADDR(DI_CHAN2_FMT_W)
#define P_VIU2_ADDR_START VPU_REG_ADDR(VIU2_ADDR_START)
#define P_VIU2_ADDR_END VPU_REG_ADDR(VIU2_ADDR_END)
#define P_VIU2_SW_RESET VPU_REG_ADDR(VIU2_SW_RESET)
#define P_VIU2_OSD1_CTRL_STAT VPU_REG_ADDR(VIU2_OSD1_CTRL_STAT)
#define P_VIU2_OSD1_CTRL_STAT2 VPU_REG_ADDR(VIU2_OSD1_CTRL_STAT2)
#define P_VIU2_OSD1_COLOR_ADDR VPU_REG_ADDR(VIU2_OSD1_COLOR_ADDR)
#define P_VIU2_OSD1_COLOR VPU_REG_ADDR(VIU2_OSD1_COLOR)
#define P_VIU2_OSD1_TCOLOR_AG0 VPU_REG_ADDR(VIU2_OSD1_TCOLOR_AG0)
#define P_VIU2_OSD1_TCOLOR_AG1 VPU_REG_ADDR(VIU2_OSD1_TCOLOR_AG1)
#define P_VIU2_OSD1_TCOLOR_AG2 VPU_REG_ADDR(VIU2_OSD1_TCOLOR_AG2)
#define P_VIU2_OSD1_TCOLOR_AG3 VPU_REG_ADDR(VIU2_OSD1_TCOLOR_AG3)
#define P_VIU2_OSD1_BLK0_CFG_W0 VPU_REG_ADDR(VIU2_OSD1_BLK0_CFG_W0)
#define P_VIU2_OSD1_BLK1_CFG_W0 VPU_REG_ADDR(VIU2_OSD1_BLK1_CFG_W0)
#define P_VIU2_OSD1_BLK2_CFG_W0 VPU_REG_ADDR(VIU2_OSD1_BLK2_CFG_W0)
#define P_VIU2_OSD1_BLK3_CFG_W0 VPU_REG_ADDR(VIU2_OSD1_BLK3_CFG_W0)
#define P_VIU2_OSD1_BLK0_CFG_W1 VPU_REG_ADDR(VIU2_OSD1_BLK0_CFG_W1)
#define P_VIU2_OSD1_BLK1_CFG_W1 VPU_REG_ADDR(VIU2_OSD1_BLK1_CFG_W1)
#define P_VIU2_OSD1_BLK2_CFG_W1 VPU_REG_ADDR(VIU2_OSD1_BLK2_CFG_W1)
#define P_VIU2_OSD1_BLK3_CFG_W1 VPU_REG_ADDR(VIU2_OSD1_BLK3_CFG_W1)
#define P_VIU2_OSD1_BLK0_CFG_W2 VPU_REG_ADDR(VIU2_OSD1_BLK0_CFG_W2)
#define P_VIU2_OSD1_BLK1_CFG_W2 VPU_REG_ADDR(VIU2_OSD1_BLK1_CFG_W2)
#define P_VIU2_OSD1_BLK2_CFG_W2 VPU_REG_ADDR(VIU2_OSD1_BLK2_CFG_W2)
#define P_VIU2_OSD1_BLK3_CFG_W2 VPU_REG_ADDR(VIU2_OSD1_BLK3_CFG_W2)
#define P_VIU2_OSD1_BLK0_CFG_W3 VPU_REG_ADDR(VIU2_OSD1_BLK0_CFG_W3)
#define P_VIU2_OSD1_BLK1_CFG_W3 VPU_REG_ADDR(VIU2_OSD1_BLK1_CFG_W3)
#define P_VIU2_OSD1_BLK2_CFG_W3 VPU_REG_ADDR(VIU2_OSD1_BLK2_CFG_W3)
#define P_VIU2_OSD1_BLK3_CFG_W3 VPU_REG_ADDR(VIU2_OSD1_BLK3_CFG_W3)
#define P_VIU2_OSD1_BLK0_CFG_W4 VPU_REG_ADDR(VIU2_OSD1_BLK0_CFG_W4)
#define P_VIU2_OSD1_BLK1_CFG_W4 VPU_REG_ADDR(VIU2_OSD1_BLK1_CFG_W4)
#define P_VIU2_OSD1_BLK2_CFG_W4 VPU_REG_ADDR(VIU2_OSD1_BLK2_CFG_W4)
#define P_VIU2_OSD1_BLK3_CFG_W4 VPU_REG_ADDR(VIU2_OSD1_BLK3_CFG_W4)
#define P_VIU2_OSD1_FIFO_CTRL_STAT VPU_REG_ADDR(VIU2_OSD1_FIFO_CTRL_STAT)
#define P_VIU2_OSD1_TEST_RDDATA VPU_REG_ADDR(VIU2_OSD1_TEST_RDDATA)
#define P_VIU2_OSD1_PROT_CTRL VPU_REG_ADDR(VIU2_OSD1_PROT_CTRL)
#define P_VIU2_OSD2_CTRL_STAT VPU_REG_ADDR(VIU2_OSD2_CTRL_STAT)
#define P_VIU2_OSD2_CTRL_STAT2 VPU_REG_ADDR(VIU2_OSD2_CTRL_STAT2)
#define P_VIU2_OSD2_COLOR_ADDR VPU_REG_ADDR(VIU2_OSD2_COLOR_ADDR)
#define P_VIU2_OSD2_COLOR VPU_REG_ADDR(VIU2_OSD2_COLOR)
#define P_VIU2_OSD2_HL1_H_START_END VPU_REG_ADDR(VIU2_OSD2_HL1_H_START_END)
#define P_VIU2_OSD2_HL1_V_START_END VPU_REG_ADDR(VIU2_OSD2_HL1_V_START_END)
#define P_VIU2_OSD2_HL2_H_START_END VPU_REG_ADDR(VIU2_OSD2_HL2_H_START_END)
#define P_VIU2_OSD2_HL2_V_START_END VPU_REG_ADDR(VIU2_OSD2_HL2_V_START_END)
#define P_VIU2_OSD2_TCOLOR_AG0 VPU_REG_ADDR(VIU2_OSD2_TCOLOR_AG0)
#define P_VIU2_OSD2_TCOLOR_AG1 VPU_REG_ADDR(VIU2_OSD2_TCOLOR_AG1)
#define P_VIU2_OSD2_TCOLOR_AG2 VPU_REG_ADDR(VIU2_OSD2_TCOLOR_AG2)
#define P_VIU2_OSD2_TCOLOR_AG3 VPU_REG_ADDR(VIU2_OSD2_TCOLOR_AG3)
#define P_VIU2_OSD2_BLK0_CFG_W0 VPU_REG_ADDR(VIU2_OSD2_BLK0_CFG_W0)
#define P_VIU2_OSD2_BLK1_CFG_W0 VPU_REG_ADDR(VIU2_OSD2_BLK1_CFG_W0)
#define P_VIU2_OSD2_BLK2_CFG_W0 VPU_REG_ADDR(VIU2_OSD2_BLK2_CFG_W0)
#define P_VIU2_OSD2_BLK3_CFG_W0 VPU_REG_ADDR(VIU2_OSD2_BLK3_CFG_W0)
#define P_VIU2_OSD2_BLK0_CFG_W1 VPU_REG_ADDR(VIU2_OSD2_BLK0_CFG_W1)
#define P_VIU2_OSD2_BLK1_CFG_W1 VPU_REG_ADDR(VIU2_OSD2_BLK1_CFG_W1)
#define P_VIU2_OSD2_BLK2_CFG_W1 VPU_REG_ADDR(VIU2_OSD2_BLK2_CFG_W1)
#define P_VIU2_OSD2_BLK3_CFG_W1 VPU_REG_ADDR(VIU2_OSD2_BLK3_CFG_W1)
#define P_VIU2_OSD2_BLK0_CFG_W2 VPU_REG_ADDR(VIU2_OSD2_BLK0_CFG_W2)
#define P_VIU2_OSD2_BLK1_CFG_W2 VPU_REG_ADDR(VIU2_OSD2_BLK1_CFG_W2)
#define P_VIU2_OSD2_BLK2_CFG_W2 VPU_REG_ADDR(VIU2_OSD2_BLK2_CFG_W2)
#define P_VIU2_OSD2_BLK3_CFG_W2 VPU_REG_ADDR(VIU2_OSD2_BLK3_CFG_W2)
#define P_VIU2_OSD2_BLK0_CFG_W3 VPU_REG_ADDR(VIU2_OSD2_BLK0_CFG_W3)
#define P_VIU2_OSD2_BLK1_CFG_W3 VPU_REG_ADDR(VIU2_OSD2_BLK1_CFG_W3)
#define P_VIU2_OSD2_BLK2_CFG_W3 VPU_REG_ADDR(VIU2_OSD2_BLK2_CFG_W3)
#define P_VIU2_OSD2_BLK3_CFG_W3 VPU_REG_ADDR(VIU2_OSD2_BLK3_CFG_W3)
#define P_VIU2_OSD2_BLK0_CFG_W4 VPU_REG_ADDR(VIU2_OSD2_BLK0_CFG_W4)
#define P_VIU2_OSD2_BLK1_CFG_W4 VPU_REG_ADDR(VIU2_OSD2_BLK1_CFG_W4)
#define P_VIU2_OSD2_BLK2_CFG_W4 VPU_REG_ADDR(VIU2_OSD2_BLK2_CFG_W4)
#define P_VIU2_OSD2_BLK3_CFG_W4 VPU_REG_ADDR(VIU2_OSD2_BLK3_CFG_W4)
#define P_VIU2_OSD2_FIFO_CTRL_STAT VPU_REG_ADDR(VIU2_OSD2_FIFO_CTRL_STAT)
#define P_VIU2_OSD2_TEST_RDDATA VPU_REG_ADDR(VIU2_OSD2_TEST_RDDATA)
#define P_VIU2_OSD2_PROT_CTRL VPU_REG_ADDR(VIU2_OSD2_PROT_CTRL)
#define P_VIU2_VD1_IF0_GEN_REG VPU_REG_ADDR(VIU2_VD1_IF0_GEN_REG)
#define P_VIU2_VD1_IF0_CANVAS0 VPU_REG_ADDR(VIU2_VD1_IF0_CANVAS0)
#define P_VIU2_VD1_IF0_CANVAS1 VPU_REG_ADDR(VIU2_VD1_IF0_CANVAS1)
#define P_VIU2_VD1_IF0_LUMA_X0 VPU_REG_ADDR(VIU2_VD1_IF0_LUMA_X0)
#define P_VIU2_VD1_IF0_LUMA_Y0 VPU_REG_ADDR(VIU2_VD1_IF0_LUMA_Y0)
#define P_VIU2_VD1_IF0_CHROMA_X0 VPU_REG_ADDR(VIU2_VD1_IF0_CHROMA_X0)
#define P_VIU2_VD1_IF0_CHROMA_Y0 VPU_REG_ADDR(VIU2_VD1_IF0_CHROMA_Y0)
#define P_VIU2_VD1_IF0_LUMA_X1 VPU_REG_ADDR(VIU2_VD1_IF0_LUMA_X1)
#define P_VIU2_VD1_IF0_LUMA_Y1 VPU_REG_ADDR(VIU2_VD1_IF0_LUMA_Y1)
#define P_VIU2_VD1_IF0_CHROMA_X1 VPU_REG_ADDR(VIU2_VD1_IF0_CHROMA_X1)
#define P_VIU2_VD1_IF0_CHROMA_Y1 VPU_REG_ADDR(VIU2_VD1_IF0_CHROMA_Y1)
#define P_VIU2_VD1_IF0_RPT_LOOP VPU_REG_ADDR(VIU2_VD1_IF0_RPT_LOOP)
#define P_VIU2_VD1_IF0_LUMA0_RPT_PAT VPU_REG_ADDR(VIU2_VD1_IF0_LUMA0_RPT_PAT)
#define P_VIU2_VD1_IF0_CHROMA0_RPT_PAT VPU_REG_ADDR(VIU2_VD1_IF0_CHROMA0_RPT_PAT)
#define P_VIU2_VD1_IF0_LUMA1_RPT_PAT VPU_REG_ADDR(VIU2_VD1_IF0_LUMA1_RPT_PAT)
#define P_VIU2_VD1_IF0_CHROMA1_RPT_PAT VPU_REG_ADDR(VIU2_VD1_IF0_CHROMA1_RPT_PAT)
#define P_VIU2_VD1_IF0_LUMA_PSEL VPU_REG_ADDR(VIU2_VD1_IF0_LUMA_PSEL)
#define P_VIU2_VD1_IF0_CHROMA_PSEL VPU_REG_ADDR(VIU2_VD1_IF0_CHROMA_PSEL)
#define P_VIU2_VD1_IF0_DUMMY_PIXEL VPU_REG_ADDR(VIU2_VD1_IF0_DUMMY_PIXEL)
#define P_VIU2_VD1_IF0_LUMA_FIFO_SIZE VPU_REG_ADDR(VIU2_VD1_IF0_LUMA_FIFO_SIZE)
#define P_VIU2_VD1_IF0_RANGE_MAP_Y VPU_REG_ADDR(VIU2_VD1_IF0_RANGE_MAP_Y)
#define P_VIU2_VD1_IF0_RANGE_MAP_CB VPU_REG_ADDR(VIU2_VD1_IF0_RANGE_MAP_CB)
#define P_VIU2_VD1_IF0_RANGE_MAP_CR VPU_REG_ADDR(VIU2_VD1_IF0_RANGE_MAP_CR)
#define P_VIU2_VD1_IF0_GEN_REG2 VPU_REG_ADDR(VIU2_VD1_IF0_GEN_REG2)
#define P_VIU2_VD1_IF0_PROT_CNTL VPU_REG_ADDR(VIU2_VD1_IF0_PROT_CNTL)
#define P_VIU2_VD1_FMT_CTRL VPU_REG_ADDR(VIU2_VD1_FMT_CTRL)
#define P_VIU2_VD1_FMT_W VPU_REG_ADDR(VIU2_VD1_FMT_W)
#define P_ENCP_VFIFO2VD_CTL VPU_REG_ADDR(ENCP_VFIFO2VD_CTL)
#define P_ENCP_VFIFO2VD_PIXEL_START VPU_REG_ADDR(ENCP_VFIFO2VD_PIXEL_START)
#define P_ENCP_VFIFO2VD_PIXEL_END VPU_REG_ADDR(ENCP_VFIFO2VD_PIXEL_END)
#define P_ENCP_VFIFO2VD_LINE_TOP_START VPU_REG_ADDR(ENCP_VFIFO2VD_LINE_TOP_START)
#define P_ENCP_VFIFO2VD_LINE_TOP_END VPU_REG_ADDR(ENCP_VFIFO2VD_LINE_TOP_END)
#define P_ENCP_VFIFO2VD_LINE_BOT_START VPU_REG_ADDR(ENCP_VFIFO2VD_LINE_BOT_START)
#define P_ENCP_VFIFO2VD_LINE_BOT_END VPU_REG_ADDR(ENCP_VFIFO2VD_LINE_BOT_END)
#define P_VENC_SYNC_ROUTE VPU_REG_ADDR(VENC_SYNC_ROUTE)
#define P_VENC_VIDEO_EXSRC VPU_REG_ADDR(VENC_VIDEO_EXSRC)
#define P_VENC_DVI_SETTING VPU_REG_ADDR(VENC_DVI_SETTING)
#define P_VENC_C656_CTRL VPU_REG_ADDR(VENC_C656_CTRL)
#define P_VENC_UPSAMPLE_CTRL0 VPU_REG_ADDR(VENC_UPSAMPLE_CTRL0)
#define P_VENC_UPSAMPLE_CTRL1 VPU_REG_ADDR(VENC_UPSAMPLE_CTRL1)
#define P_VENC_UPSAMPLE_CTRL2 VPU_REG_ADDR(VENC_UPSAMPLE_CTRL2)
#define P_TCON_INVERT_CTL VPU_REG_ADDR(TCON_INVERT_CTL)
#define P_VENC_VIDEO_PROG_MODE VPU_REG_ADDR(VENC_VIDEO_PROG_MODE)
#define P_VENC_ENCI_LINE VPU_REG_ADDR(VENC_ENCI_LINE)
#define P_VENC_ENCI_PIXEL VPU_REG_ADDR(VENC_ENCI_PIXEL)
#define P_VENC_ENCP_LINE VPU_REG_ADDR(VENC_ENCP_LINE)
#define P_VENC_ENCP_PIXEL VPU_REG_ADDR(VENC_ENCP_PIXEL)
#define P_VENC_STATA VPU_REG_ADDR(VENC_STATA)
#define P_VENC_INTCTRL VPU_REG_ADDR(VENC_INTCTRL)
#define P_VENC_INTFLAG VPU_REG_ADDR(VENC_INTFLAG)
#define P_VENC_VIDEO_TST_EN VPU_REG_ADDR(VENC_VIDEO_TST_EN)
#define P_VENC_VIDEO_TST_MDSEL VPU_REG_ADDR(VENC_VIDEO_TST_MDSEL)
#define P_VENC_VIDEO_TST_Y VPU_REG_ADDR(VENC_VIDEO_TST_Y)
#define P_VENC_VIDEO_TST_CB VPU_REG_ADDR(VENC_VIDEO_TST_CB)
#define P_VENC_VIDEO_TST_CR VPU_REG_ADDR(VENC_VIDEO_TST_CR)
#define P_VENC_VIDEO_TST_CLRBAR_STRT VPU_REG_ADDR(VENC_VIDEO_TST_CLRBAR_STRT)
#define P_VENC_VIDEO_TST_CLRBAR_WIDTH VPU_REG_ADDR(VENC_VIDEO_TST_CLRBAR_WIDTH)
#define P_VENC_VIDEO_TST_VDCNT_STSET VPU_REG_ADDR(VENC_VIDEO_TST_VDCNT_STSET)
#define P_VENC_VDAC_DACSEL0 VPU_REG_ADDR(VENC_VDAC_DACSEL0)
#define P_VENC_VDAC_DACSEL1 VPU_REG_ADDR(VENC_VDAC_DACSEL1)
#define P_VENC_VDAC_DACSEL2 VPU_REG_ADDR(VENC_VDAC_DACSEL2)
#define P_VENC_VDAC_DACSEL3 VPU_REG_ADDR(VENC_VDAC_DACSEL3)
#define P_VENC_VDAC_DACSEL4 VPU_REG_ADDR(VENC_VDAC_DACSEL4)
#define P_VENC_VDAC_DACSEL5 VPU_REG_ADDR(VENC_VDAC_DACSEL5)
#define P_VENC_VDAC_SETTING VPU_REG_ADDR(VENC_VDAC_SETTING)
#define P_VENC_VDAC_TST_VAL VPU_REG_ADDR(VENC_VDAC_TST_VAL)
#define P_VENC_VDAC_DAC0_GAINCTRL VPU_REG_ADDR(VENC_VDAC_DAC0_GAINCTRL)
#define P_VENC_VDAC_DAC0_OFFSET VPU_REG_ADDR(VENC_VDAC_DAC0_OFFSET)
#define P_VENC_VDAC_DAC1_GAINCTRL VPU_REG_ADDR(VENC_VDAC_DAC1_GAINCTRL)
#define P_VENC_VDAC_DAC1_OFFSET VPU_REG_ADDR(VENC_VDAC_DAC1_OFFSET)
#define P_VENC_VDAC_DAC2_GAINCTRL VPU_REG_ADDR(VENC_VDAC_DAC2_GAINCTRL)
#define P_VENC_VDAC_DAC2_OFFSET VPU_REG_ADDR(VENC_VDAC_DAC2_OFFSET)
#define P_VENC_VDAC_DAC3_GAINCTRL VPU_REG_ADDR(VENC_VDAC_DAC3_GAINCTRL)
#define P_VENC_VDAC_DAC3_OFFSET VPU_REG_ADDR(VENC_VDAC_DAC3_OFFSET)
#define P_VENC_VDAC_DAC4_GAINCTRL VPU_REG_ADDR(VENC_VDAC_DAC4_GAINCTRL)
#define P_VENC_VDAC_DAC4_OFFSET VPU_REG_ADDR(VENC_VDAC_DAC4_OFFSET)
#define P_VENC_VDAC_DAC5_GAINCTRL VPU_REG_ADDR(VENC_VDAC_DAC5_GAINCTRL)
#define P_VENC_VDAC_DAC5_OFFSET VPU_REG_ADDR(VENC_VDAC_DAC5_OFFSET)
#define P_VENC_VDAC_FIFO_CTRL VPU_REG_ADDR(VENC_VDAC_FIFO_CTRL)
#define P_ENCL_TCON_INVERT_CTL VPU_REG_ADDR(ENCL_TCON_INVERT_CTL)
#define P_ENCP_VIDEO_EN VPU_REG_ADDR(ENCP_VIDEO_EN)
#define P_ENCP_VIDEO_SYNC_MODE VPU_REG_ADDR(ENCP_VIDEO_SYNC_MODE)
#define P_ENCP_MACV_EN VPU_REG_ADDR(ENCP_MACV_EN)
#define P_ENCP_VIDEO_Y_SCL VPU_REG_ADDR(ENCP_VIDEO_Y_SCL)
#define P_ENCP_VIDEO_PB_SCL VPU_REG_ADDR(ENCP_VIDEO_PB_SCL)
#define P_ENCP_VIDEO_PR_SCL VPU_REG_ADDR(ENCP_VIDEO_PR_SCL)
#define P_ENCP_VIDEO_SYNC_SCL VPU_REG_ADDR(ENCP_VIDEO_SYNC_SCL)
#define P_ENCP_VIDEO_MACV_SCL VPU_REG_ADDR(ENCP_VIDEO_MACV_SCL)
#define P_ENCP_VIDEO_Y_OFFST VPU_REG_ADDR(ENCP_VIDEO_Y_OFFST)
#define P_ENCP_VIDEO_PB_OFFST VPU_REG_ADDR(ENCP_VIDEO_PB_OFFST)
#define P_ENCP_VIDEO_PR_OFFST VPU_REG_ADDR(ENCP_VIDEO_PR_OFFST)
#define P_ENCP_VIDEO_SYNC_OFFST VPU_REG_ADDR(ENCP_VIDEO_SYNC_OFFST)
#define P_ENCP_VIDEO_MACV_OFFST VPU_REG_ADDR(ENCP_VIDEO_MACV_OFFST)
#define P_ENCP_VIDEO_MODE VPU_REG_ADDR(ENCP_VIDEO_MODE)
#define P_ENCP_VIDEO_MODE_ADV VPU_REG_ADDR(ENCP_VIDEO_MODE_ADV)
#define P_ENCP_DBG_PX_RST VPU_REG_ADDR(ENCP_DBG_PX_RST)
#define P_ENCP_DBG_LN_RST VPU_REG_ADDR(ENCP_DBG_LN_RST)
#define P_ENCP_DBG_PX_INT VPU_REG_ADDR(ENCP_DBG_PX_INT)
#define P_ENCP_DBG_LN_INT VPU_REG_ADDR(ENCP_DBG_LN_INT)
#define P_ENCP_VIDEO_YFP1_HTIME VPU_REG_ADDR(ENCP_VIDEO_YFP1_HTIME)
#define P_ENCP_VIDEO_YFP2_HTIME VPU_REG_ADDR(ENCP_VIDEO_YFP2_HTIME)
#define P_ENCP_VIDEO_YC_DLY VPU_REG_ADDR(ENCP_VIDEO_YC_DLY)
#define P_ENCP_VIDEO_MAX_PXCNT VPU_REG_ADDR(ENCP_VIDEO_MAX_PXCNT)
#define P_ENCP_VIDEO_HSPULS_BEGIN VPU_REG_ADDR(ENCP_VIDEO_HSPULS_BEGIN)
#define P_ENCP_VIDEO_HSPULS_END VPU_REG_ADDR(ENCP_VIDEO_HSPULS_END)
#define P_ENCP_VIDEO_HSPULS_SWITCH VPU_REG_ADDR(ENCP_VIDEO_HSPULS_SWITCH)
#define P_ENCP_VIDEO_VSPULS_BEGIN VPU_REG_ADDR(ENCP_VIDEO_VSPULS_BEGIN)
#define P_ENCP_VIDEO_VSPULS_END VPU_REG_ADDR(ENCP_VIDEO_VSPULS_END)
#define P_ENCP_VIDEO_VSPULS_BLINE VPU_REG_ADDR(ENCP_VIDEO_VSPULS_BLINE)
#define P_ENCP_VIDEO_VSPULS_ELINE VPU_REG_ADDR(ENCP_VIDEO_VSPULS_ELINE)
#define P_ENCP_VIDEO_EQPULS_BEGIN VPU_REG_ADDR(ENCP_VIDEO_EQPULS_BEGIN)
#define P_ENCP_VIDEO_EQPULS_END VPU_REG_ADDR(ENCP_VIDEO_EQPULS_END)
#define P_ENCP_VIDEO_EQPULS_BLINE VPU_REG_ADDR(ENCP_VIDEO_EQPULS_BLINE)
#define P_ENCP_VIDEO_EQPULS_ELINE VPU_REG_ADDR(ENCP_VIDEO_EQPULS_ELINE)
#define P_ENCP_VIDEO_HAVON_END VPU_REG_ADDR(ENCP_VIDEO_HAVON_END)
#define P_ENCP_VIDEO_HAVON_BEGIN VPU_REG_ADDR(ENCP_VIDEO_HAVON_BEGIN)
#define P_ENCP_VIDEO_VAVON_ELINE VPU_REG_ADDR(ENCP_VIDEO_VAVON_ELINE)
#define P_ENCP_VIDEO_VAVON_BLINE VPU_REG_ADDR(ENCP_VIDEO_VAVON_BLINE)
#define P_ENCP_VIDEO_HSO_BEGIN VPU_REG_ADDR(ENCP_VIDEO_HSO_BEGIN)
#define P_ENCP_VIDEO_HSO_END VPU_REG_ADDR(ENCP_VIDEO_HSO_END)
#define P_ENCP_VIDEO_VSO_BEGIN VPU_REG_ADDR(ENCP_VIDEO_VSO_BEGIN)
#define P_ENCP_VIDEO_VSO_END VPU_REG_ADDR(ENCP_VIDEO_VSO_END)
#define P_ENCP_VIDEO_VSO_BLINE VPU_REG_ADDR(ENCP_VIDEO_VSO_BLINE)
#define P_ENCP_VIDEO_VSO_ELINE VPU_REG_ADDR(ENCP_VIDEO_VSO_ELINE)
#define P_ENCP_VIDEO_SYNC_WAVE_CURVE VPU_REG_ADDR(ENCP_VIDEO_SYNC_WAVE_CURVE)
#define P_ENCP_VIDEO_MAX_LNCNT VPU_REG_ADDR(ENCP_VIDEO_MAX_LNCNT)
#define P_ENCP_VIDEO_SY_VAL VPU_REG_ADDR(ENCP_VIDEO_SY_VAL)
#define P_ENCP_VIDEO_SY2_VAL VPU_REG_ADDR(ENCP_VIDEO_SY2_VAL)
#define P_ENCP_VIDEO_BLANKY_VAL VPU_REG_ADDR(ENCP_VIDEO_BLANKY_VAL)
#define P_ENCP_VIDEO_BLANKPB_VAL VPU_REG_ADDR(ENCP_VIDEO_BLANKPB_VAL)
#define P_ENCP_VIDEO_BLANKPR_VAL VPU_REG_ADDR(ENCP_VIDEO_BLANKPR_VAL)
#define P_ENCP_VIDEO_HOFFST VPU_REG_ADDR(ENCP_VIDEO_HOFFST)
#define P_ENCP_VIDEO_VOFFST VPU_REG_ADDR(ENCP_VIDEO_VOFFST)
#define P_ENCP_VIDEO_RGB_CTRL VPU_REG_ADDR(ENCP_VIDEO_RGB_CTRL)
#define P_ENCP_VIDEO_FILT_CTRL VPU_REG_ADDR(ENCP_VIDEO_FILT_CTRL)
#define P_ENCP_VIDEO_OFLD_VPEQ_OFST VPU_REG_ADDR(ENCP_VIDEO_OFLD_VPEQ_OFST)
#define P_ENCP_VIDEO_OFLD_VOAV_OFST VPU_REG_ADDR(ENCP_VIDEO_OFLD_VOAV_OFST)
#define P_ENCP_VIDEO_MATRIX_CB VPU_REG_ADDR(ENCP_VIDEO_MATRIX_CB)
#define P_ENCP_VIDEO_MATRIX_CR VPU_REG_ADDR(ENCP_VIDEO_MATRIX_CR)
#define P_ENCP_VIDEO_RGBIN_CTRL VPU_REG_ADDR(ENCP_VIDEO_RGBIN_CTRL)
#define P_ENCP_MACV_BLANKY_VAL VPU_REG_ADDR(ENCP_MACV_BLANKY_VAL)
#define P_ENCP_MACV_MAXY_VAL VPU_REG_ADDR(ENCP_MACV_MAXY_VAL)
#define P_ENCP_MACV_1ST_PSSYNC_STRT VPU_REG_ADDR(ENCP_MACV_1ST_PSSYNC_STRT)
#define P_ENCP_MACV_PSSYNC_STRT VPU_REG_ADDR(ENCP_MACV_PSSYNC_STRT)
#define P_ENCP_MACV_AGC_STRT VPU_REG_ADDR(ENCP_MACV_AGC_STRT)
#define P_ENCP_MACV_AGC_END VPU_REG_ADDR(ENCP_MACV_AGC_END)
#define P_ENCP_MACV_WAVE_END VPU_REG_ADDR(ENCP_MACV_WAVE_END)
#define P_ENCP_MACV_STRTLINE VPU_REG_ADDR(ENCP_MACV_STRTLINE)
#define P_ENCP_MACV_ENDLINE VPU_REG_ADDR(ENCP_MACV_ENDLINE)
#define P_ENCP_MACV_TS_CNT_MAX_L VPU_REG_ADDR(ENCP_MACV_TS_CNT_MAX_L)
#define P_ENCP_MACV_TS_CNT_MAX_H VPU_REG_ADDR(ENCP_MACV_TS_CNT_MAX_H)
#define P_ENCP_MACV_TIME_DOWN VPU_REG_ADDR(ENCP_MACV_TIME_DOWN)
#define P_ENCP_MACV_TIME_LO VPU_REG_ADDR(ENCP_MACV_TIME_LO)
#define P_ENCP_MACV_TIME_UP VPU_REG_ADDR(ENCP_MACV_TIME_UP)
#define P_ENCP_MACV_TIME_RST VPU_REG_ADDR(ENCP_MACV_TIME_RST)
#define P_ENCP_VBI_CTRL VPU_REG_ADDR(ENCP_VBI_CTRL)
#define P_ENCP_VBI_SETTING VPU_REG_ADDR(ENCP_VBI_SETTING)
#define P_ENCP_VBI_BEGIN VPU_REG_ADDR(ENCP_VBI_BEGIN)
#define P_ENCP_VBI_WIDTH VPU_REG_ADDR(ENCP_VBI_WIDTH)
#define P_ENCP_VBI_HVAL VPU_REG_ADDR(ENCP_VBI_HVAL)
#define P_ENCP_VBI_DATA0 VPU_REG_ADDR(ENCP_VBI_DATA0)
#define P_ENCP_VBI_DATA1 VPU_REG_ADDR(ENCP_VBI_DATA1)
#define P_C656_HS_ST VPU_REG_ADDR(C656_HS_ST)
#define P_C656_HS_ED VPU_REG_ADDR(C656_HS_ED)
#define P_C656_VS_LNST_E VPU_REG_ADDR(C656_VS_LNST_E)
#define P_C656_VS_LNST_O VPU_REG_ADDR(C656_VS_LNST_O)
#define P_C656_VS_LNED_E VPU_REG_ADDR(C656_VS_LNED_E)
#define P_C656_VS_LNED_O VPU_REG_ADDR(C656_VS_LNED_O)
#define P_C656_FS_LNST VPU_REG_ADDR(C656_FS_LNST)
#define P_C656_FS_LNED VPU_REG_ADDR(C656_FS_LNED)
#define P_ENCI_VIDEO_MODE VPU_REG_ADDR(ENCI_VIDEO_MODE)
#define P_ENCI_VIDEO_MODE_ADV VPU_REG_ADDR(ENCI_VIDEO_MODE_ADV)
#define P_ENCI_VIDEO_FSC_ADJ VPU_REG_ADDR(ENCI_VIDEO_FSC_ADJ)
#define P_ENCI_VIDEO_BRIGHT VPU_REG_ADDR(ENCI_VIDEO_BRIGHT)
#define P_ENCI_VIDEO_CONT VPU_REG_ADDR(ENCI_VIDEO_CONT)
#define P_ENCI_VIDEO_SAT VPU_REG_ADDR(ENCI_VIDEO_SAT)
#define P_ENCI_VIDEO_HUE VPU_REG_ADDR(ENCI_VIDEO_HUE)
#define P_ENCI_VIDEO_SCH VPU_REG_ADDR(ENCI_VIDEO_SCH)
#define P_ENCI_SYNC_MODE VPU_REG_ADDR(ENCI_SYNC_MODE)
#define P_ENCI_SYNC_CTRL VPU_REG_ADDR(ENCI_SYNC_CTRL)
#define P_ENCI_SYNC_HSO_BEGIN VPU_REG_ADDR(ENCI_SYNC_HSO_BEGIN)
#define P_ENCI_SYNC_HSO_END VPU_REG_ADDR(ENCI_SYNC_HSO_END)
#define P_ENCI_SYNC_VSO_EVN VPU_REG_ADDR(ENCI_SYNC_VSO_EVN)
#define P_ENCI_SYNC_VSO_ODD VPU_REG_ADDR(ENCI_SYNC_VSO_ODD)
#define P_ENCI_SYNC_VSO_EVNLN VPU_REG_ADDR(ENCI_SYNC_VSO_EVNLN)
#define P_ENCI_SYNC_VSO_ODDLN VPU_REG_ADDR(ENCI_SYNC_VSO_ODDLN)
#define P_ENCI_SYNC_HOFFST VPU_REG_ADDR(ENCI_SYNC_HOFFST)
#define P_ENCI_SYNC_VOFFST VPU_REG_ADDR(ENCI_SYNC_VOFFST)
#define P_ENCI_SYNC_ADJ VPU_REG_ADDR(ENCI_SYNC_ADJ)
#define P_ENCI_RGB_SETTING VPU_REG_ADDR(ENCI_RGB_SETTING)
#define P_ENCI_DE_H_BEGIN VPU_REG_ADDR(ENCI_DE_H_BEGIN)
#define P_ENCI_DE_H_END VPU_REG_ADDR(ENCI_DE_H_END)
#define P_ENCI_DE_V_BEGIN_EVEN VPU_REG_ADDR(ENCI_DE_V_BEGIN_EVEN)
#define P_ENCI_DE_V_END_EVEN VPU_REG_ADDR(ENCI_DE_V_END_EVEN)
#define P_ENCI_DE_V_BEGIN_ODD VPU_REG_ADDR(ENCI_DE_V_BEGIN_ODD)
#define P_ENCI_DE_V_END_ODD VPU_REG_ADDR(ENCI_DE_V_END_ODD)
#define P_ENCI_VBI_SETTING VPU_REG_ADDR(ENCI_VBI_SETTING)
#define P_ENCI_VBI_CCDT_EVN VPU_REG_ADDR(ENCI_VBI_CCDT_EVN)
#define P_ENCI_VBI_CCDT_ODD VPU_REG_ADDR(ENCI_VBI_CCDT_ODD)
#define P_ENCI_VBI_CC525_LN VPU_REG_ADDR(ENCI_VBI_CC525_LN)
#define P_ENCI_VBI_CC625_LN VPU_REG_ADDR(ENCI_VBI_CC625_LN)
#define P_ENCI_VBI_WSSDT VPU_REG_ADDR(ENCI_VBI_WSSDT)
#define P_ENCI_VBI_WSS_LN VPU_REG_ADDR(ENCI_VBI_WSS_LN)
#define P_ENCI_VBI_CGMSDT_L VPU_REG_ADDR(ENCI_VBI_CGMSDT_L)
#define P_ENCI_VBI_CGMSDT_H VPU_REG_ADDR(ENCI_VBI_CGMSDT_H)
#define P_ENCI_VBI_CGMS_LN VPU_REG_ADDR(ENCI_VBI_CGMS_LN)
#define P_ENCI_VBI_TTX_HTIME VPU_REG_ADDR(ENCI_VBI_TTX_HTIME)
#define P_ENCI_VBI_TTX_LN VPU_REG_ADDR(ENCI_VBI_TTX_LN)
#define P_ENCI_VBI_TTXDT0 VPU_REG_ADDR(ENCI_VBI_TTXDT0)
#define P_ENCI_VBI_TTXDT1 VPU_REG_ADDR(ENCI_VBI_TTXDT1)
#define P_ENCI_VBI_TTXDT2 VPU_REG_ADDR(ENCI_VBI_TTXDT2)
#define P_ENCI_VBI_TTXDT3 VPU_REG_ADDR(ENCI_VBI_TTXDT3)
#define P_ENCI_MACV_N0 VPU_REG_ADDR(ENCI_MACV_N0)
#define P_ENCI_MACV_N1 VPU_REG_ADDR(ENCI_MACV_N1)
#define P_ENCI_MACV_N2 VPU_REG_ADDR(ENCI_MACV_N2)
#define P_ENCI_MACV_N3 VPU_REG_ADDR(ENCI_MACV_N3)
#define P_ENCI_MACV_N4 VPU_REG_ADDR(ENCI_MACV_N4)
#define P_ENCI_MACV_N5 VPU_REG_ADDR(ENCI_MACV_N5)
#define P_ENCI_MACV_N6 VPU_REG_ADDR(ENCI_MACV_N6)
#define P_ENCI_MACV_N7 VPU_REG_ADDR(ENCI_MACV_N7)
#define P_ENCI_MACV_N8 VPU_REG_ADDR(ENCI_MACV_N8)
#define P_ENCI_MACV_N9 VPU_REG_ADDR(ENCI_MACV_N9)
#define P_ENCI_MACV_N10 VPU_REG_ADDR(ENCI_MACV_N10)
#define P_ENCI_MACV_N11 VPU_REG_ADDR(ENCI_MACV_N11)
#define P_ENCI_MACV_N12 VPU_REG_ADDR(ENCI_MACV_N12)
#define P_ENCI_MACV_N13 VPU_REG_ADDR(ENCI_MACV_N13)
#define P_ENCI_MACV_N14 VPU_REG_ADDR(ENCI_MACV_N14)
#define P_ENCI_MACV_N15 VPU_REG_ADDR(ENCI_MACV_N15)
#define P_ENCI_MACV_N16 VPU_REG_ADDR(ENCI_MACV_N16)
#define P_ENCI_MACV_N17 VPU_REG_ADDR(ENCI_MACV_N17)
#define P_ENCI_MACV_N18 VPU_REG_ADDR(ENCI_MACV_N18)
#define P_ENCI_MACV_N19 VPU_REG_ADDR(ENCI_MACV_N19)
#define P_ENCI_MACV_N20 VPU_REG_ADDR(ENCI_MACV_N20)
#define P_ENCI_MACV_N21 VPU_REG_ADDR(ENCI_MACV_N21)
#define P_ENCI_MACV_N22 VPU_REG_ADDR(ENCI_MACV_N22)
#define P_ENCI_DBG_PX_RST VPU_REG_ADDR(ENCI_DBG_PX_RST)
#define P_ENCI_DBG_FLDLN_RST VPU_REG_ADDR(ENCI_DBG_FLDLN_RST)
#define P_ENCI_DBG_PX_INT VPU_REG_ADDR(ENCI_DBG_PX_INT)
#define P_ENCI_DBG_FLDLN_INT VPU_REG_ADDR(ENCI_DBG_FLDLN_INT)
#define P_ENCI_DBG_MAXPX VPU_REG_ADDR(ENCI_DBG_MAXPX)
#define P_ENCI_DBG_MAXLN VPU_REG_ADDR(ENCI_DBG_MAXLN)
#define P_ENCI_MACV_MAX_AMP VPU_REG_ADDR(ENCI_MACV_MAX_AMP)
#define P_ENCI_MACV_PULSE_LO VPU_REG_ADDR(ENCI_MACV_PULSE_LO)
#define P_ENCI_MACV_PULSE_HI VPU_REG_ADDR(ENCI_MACV_PULSE_HI)
#define P_ENCI_MACV_BKP_MAX VPU_REG_ADDR(ENCI_MACV_BKP_MAX)
#define P_ENCI_CFILT_CTRL VPU_REG_ADDR(ENCI_CFILT_CTRL)
#define P_ENCI_CFILT7 VPU_REG_ADDR(ENCI_CFILT7)
#define P_ENCI_YC_DELAY VPU_REG_ADDR(ENCI_YC_DELAY)
#define P_ENCI_VIDEO_EN VPU_REG_ADDR(ENCI_VIDEO_EN)
#define P_ENCI_DVI_HSO_BEGIN VPU_REG_ADDR(ENCI_DVI_HSO_BEGIN)
#define P_ENCI_DVI_HSO_END VPU_REG_ADDR(ENCI_DVI_HSO_END)
#define P_ENCI_DVI_VSO_BLINE_EVN VPU_REG_ADDR(ENCI_DVI_VSO_BLINE_EVN)
#define P_ENCI_DVI_VSO_BLINE_ODD VPU_REG_ADDR(ENCI_DVI_VSO_BLINE_ODD)
#define P_ENCI_DVI_VSO_ELINE_EVN VPU_REG_ADDR(ENCI_DVI_VSO_ELINE_EVN)
#define P_ENCI_DVI_VSO_ELINE_ODD VPU_REG_ADDR(ENCI_DVI_VSO_ELINE_ODD)
#define P_ENCI_DVI_VSO_BEGIN_EVN VPU_REG_ADDR(ENCI_DVI_VSO_BEGIN_EVN)
#define P_ENCI_DVI_VSO_BEGIN_ODD VPU_REG_ADDR(ENCI_DVI_VSO_BEGIN_ODD)
#define P_ENCI_DVI_VSO_END_EVN VPU_REG_ADDR(ENCI_DVI_VSO_END_EVN)
#define P_ENCI_DVI_VSO_END_ODD VPU_REG_ADDR(ENCI_DVI_VSO_END_ODD)
#define P_ENCI_CFILT_CTRL2 VPU_REG_ADDR(ENCI_CFILT_CTRL2)
#define P_ENCI_DACSEL_0 VPU_REG_ADDR(ENCI_DACSEL_0)
#define P_ENCI_DACSEL_1 VPU_REG_ADDR(ENCI_DACSEL_1)
#define P_ENCP_DACSEL_0 VPU_REG_ADDR(ENCP_DACSEL_0)
#define P_ENCP_DACSEL_1 VPU_REG_ADDR(ENCP_DACSEL_1)
#define P_ENCP_MAX_LINE_SWITCH_POINT VPU_REG_ADDR(ENCP_MAX_LINE_SWITCH_POINT)
#define P_ENCI_TST_EN VPU_REG_ADDR(ENCI_TST_EN)
#define P_ENCI_TST_MDSEL VPU_REG_ADDR(ENCI_TST_MDSEL)
#define P_ENCI_TST_Y VPU_REG_ADDR(ENCI_TST_Y)
#define P_ENCI_TST_CB VPU_REG_ADDR(ENCI_TST_CB)
#define P_ENCI_TST_CR VPU_REG_ADDR(ENCI_TST_CR)
#define P_ENCI_TST_CLRBAR_STRT VPU_REG_ADDR(ENCI_TST_CLRBAR_STRT)
#define P_ENCI_TST_CLRBAR_WIDTH VPU_REG_ADDR(ENCI_TST_CLRBAR_WIDTH)
#define P_ENCI_TST_VDCNT_STSET VPU_REG_ADDR(ENCI_TST_VDCNT_STSET)
#define P_ENCI_VFIFO2VD_CTL VPU_REG_ADDR(ENCI_VFIFO2VD_CTL)
#define P_ENCI_VFIFO2VD_PIXEL_START VPU_REG_ADDR(ENCI_VFIFO2VD_PIXEL_START)
#define P_ENCI_VFIFO2VD_PIXEL_END VPU_REG_ADDR(ENCI_VFIFO2VD_PIXEL_END)
#define P_ENCI_VFIFO2VD_LINE_TOP_START VPU_REG_ADDR(ENCI_VFIFO2VD_LINE_TOP_START)
#define P_ENCI_VFIFO2VD_LINE_TOP_END VPU_REG_ADDR(ENCI_VFIFO2VD_LINE_TOP_END)
#define P_ENCI_VFIFO2VD_LINE_BOT_START VPU_REG_ADDR(ENCI_VFIFO2VD_LINE_BOT_START)
#define P_ENCI_VFIFO2VD_LINE_BOT_END VPU_REG_ADDR(ENCI_VFIFO2VD_LINE_BOT_END)
#define P_ENCI_VFIFO2VD_CTL2 VPU_REG_ADDR(ENCI_VFIFO2VD_CTL2)
#define P_ENCT_VFIFO2VD_CTL VPU_REG_ADDR(ENCT_VFIFO2VD_CTL)
#define P_ENCT_VFIFO2VD_PIXEL_START VPU_REG_ADDR(ENCT_VFIFO2VD_PIXEL_START)
#define P_ENCT_VFIFO2VD_PIXEL_END VPU_REG_ADDR(ENCT_VFIFO2VD_PIXEL_END)
#define P_ENCT_VFIFO2VD_LINE_TOP_START VPU_REG_ADDR(ENCT_VFIFO2VD_LINE_TOP_START)
#define P_ENCT_VFIFO2VD_LINE_TOP_END VPU_REG_ADDR(ENCT_VFIFO2VD_LINE_TOP_END)
#define P_ENCT_VFIFO2VD_LINE_BOT_START VPU_REG_ADDR(ENCT_VFIFO2VD_LINE_BOT_START)
#define P_ENCT_VFIFO2VD_LINE_BOT_END VPU_REG_ADDR(ENCT_VFIFO2VD_LINE_BOT_END)
#define P_ENCT_VFIFO2VD_CTL2 VPU_REG_ADDR(ENCT_VFIFO2VD_CTL2)
#define P_ENCT_TST_EN VPU_REG_ADDR(ENCT_TST_EN)
#define P_ENCT_TST_MDSEL VPU_REG_ADDR(ENCT_TST_MDSEL)
#define P_ENCT_TST_Y VPU_REG_ADDR(ENCT_TST_Y)
#define P_ENCT_TST_CB VPU_REG_ADDR(ENCT_TST_CB)
#define P_ENCT_TST_CR VPU_REG_ADDR(ENCT_TST_CR)
#define P_ENCT_TST_CLRBAR_STRT VPU_REG_ADDR(ENCT_TST_CLRBAR_STRT)
#define P_ENCT_TST_CLRBAR_WIDTH VPU_REG_ADDR(ENCT_TST_CLRBAR_WIDTH)
#define P_ENCT_TST_VDCNT_STSET VPU_REG_ADDR(ENCT_TST_VDCNT_STSET)
#define P_ENCP_DVI_HSO_BEGIN VPU_REG_ADDR(ENCP_DVI_HSO_BEGIN)
#define P_ENCP_DVI_HSO_END VPU_REG_ADDR(ENCP_DVI_HSO_END)
#define P_ENCP_DVI_VSO_BLINE_EVN VPU_REG_ADDR(ENCP_DVI_VSO_BLINE_EVN)
#define P_ENCP_DVI_VSO_BLINE_ODD VPU_REG_ADDR(ENCP_DVI_VSO_BLINE_ODD)
#define P_ENCP_DVI_VSO_ELINE_EVN VPU_REG_ADDR(ENCP_DVI_VSO_ELINE_EVN)
#define P_ENCP_DVI_VSO_ELINE_ODD VPU_REG_ADDR(ENCP_DVI_VSO_ELINE_ODD)
#define P_ENCP_DVI_VSO_BEGIN_EVN VPU_REG_ADDR(ENCP_DVI_VSO_BEGIN_EVN)
#define P_ENCP_DVI_VSO_BEGIN_ODD VPU_REG_ADDR(ENCP_DVI_VSO_BEGIN_ODD)
#define P_ENCP_DVI_VSO_END_EVN VPU_REG_ADDR(ENCP_DVI_VSO_END_EVN)
#define P_ENCP_DVI_VSO_END_ODD VPU_REG_ADDR(ENCP_DVI_VSO_END_ODD)
#define P_ENCP_DE_H_BEGIN VPU_REG_ADDR(ENCP_DE_H_BEGIN)
#define P_ENCP_DE_H_END VPU_REG_ADDR(ENCP_DE_H_END)
#define P_ENCP_DE_V_BEGIN_EVEN VPU_REG_ADDR(ENCP_DE_V_BEGIN_EVEN)
#define P_ENCP_DE_V_END_EVEN VPU_REG_ADDR(ENCP_DE_V_END_EVEN)
#define P_ENCP_DE_V_BEGIN_ODD VPU_REG_ADDR(ENCP_DE_V_BEGIN_ODD)
#define P_ENCP_DE_V_END_ODD VPU_REG_ADDR(ENCP_DE_V_END_ODD)
#define P_ENCI_SYNC_LINE_LENGTH VPU_REG_ADDR(ENCI_SYNC_LINE_LENGTH)
#define P_ENCI_SYNC_PIXEL_EN VPU_REG_ADDR(ENCI_SYNC_PIXEL_EN)
#define P_ENCI_SYNC_TO_LINE_EN VPU_REG_ADDR(ENCI_SYNC_TO_LINE_EN)
#define P_ENCI_SYNC_TO_PIXEL VPU_REG_ADDR(ENCI_SYNC_TO_PIXEL)
#define P_ENCP_SYNC_LINE_LENGTH VPU_REG_ADDR(ENCP_SYNC_LINE_LENGTH)
#define P_ENCP_SYNC_PIXEL_EN VPU_REG_ADDR(ENCP_SYNC_PIXEL_EN)
#define P_ENCP_SYNC_TO_LINE_EN VPU_REG_ADDR(ENCP_SYNC_TO_LINE_EN)
#define P_ENCP_SYNC_TO_PIXEL VPU_REG_ADDR(ENCP_SYNC_TO_PIXEL)
#define P_ENCT_SYNC_LINE_LENGTH VPU_REG_ADDR(ENCT_SYNC_LINE_LENGTH)
#define P_ENCT_SYNC_PIXEL_EN VPU_REG_ADDR(ENCT_SYNC_PIXEL_EN)
#define P_ENCT_SYNC_TO_LINE_EN VPU_REG_ADDR(ENCT_SYNC_TO_LINE_EN)
#define P_ENCT_SYNC_TO_PIXEL VPU_REG_ADDR(ENCT_SYNC_TO_PIXEL)
#define P_ENCL_SYNC_LINE_LENGTH VPU_REG_ADDR(ENCL_SYNC_LINE_LENGTH)
#define P_ENCL_SYNC_PIXEL_EN VPU_REG_ADDR(ENCL_SYNC_PIXEL_EN)
#define P_ENCL_SYNC_TO_LINE_EN VPU_REG_ADDR(ENCL_SYNC_TO_LINE_EN)
#define P_ENCL_SYNC_TO_PIXEL VPU_REG_ADDR(ENCL_SYNC_TO_PIXEL)
#define P_ENCP_VFIFO2VD_CTL2 VPU_REG_ADDR(ENCP_VFIFO2VD_CTL2)
#define P_VENC_DVI_SETTING_MORE VPU_REG_ADDR(VENC_DVI_SETTING_MORE)
#define P_VENC_VDAC_DAC4_FILT_CTRL0 VPU_REG_ADDR(VENC_VDAC_DAC4_FILT_CTRL0)
#define P_VENC_VDAC_DAC4_FILT_CTRL1 VPU_REG_ADDR(VENC_VDAC_DAC4_FILT_CTRL1)
#define P_VENC_VDAC_DAC5_FILT_CTRL0 VPU_REG_ADDR(VENC_VDAC_DAC5_FILT_CTRL0)
#define P_VENC_VDAC_DAC5_FILT_CTRL1 VPU_REG_ADDR(VENC_VDAC_DAC5_FILT_CTRL1)
#define P_VENC_VDAC_DAC0_FILT_CTRL0 VPU_REG_ADDR(VENC_VDAC_DAC0_FILT_CTRL0)
#define P_VENC_VDAC_DAC0_FILT_CTRL1 VPU_REG_ADDR(VENC_VDAC_DAC0_FILT_CTRL1)
#define P_VENC_VDAC_DAC1_FILT_CTRL0 VPU_REG_ADDR(VENC_VDAC_DAC1_FILT_CTRL0)
#define P_VENC_VDAC_DAC1_FILT_CTRL1 VPU_REG_ADDR(VENC_VDAC_DAC1_FILT_CTRL1)
#define P_VENC_VDAC_DAC2_FILT_CTRL0 VPU_REG_ADDR(VENC_VDAC_DAC2_FILT_CTRL0)
#define P_VENC_VDAC_DAC2_FILT_CTRL1 VPU_REG_ADDR(VENC_VDAC_DAC2_FILT_CTRL1)
#define P_VENC_VDAC_DAC3_FILT_CTRL0 VPU_REG_ADDR(VENC_VDAC_DAC3_FILT_CTRL0)
#define P_VENC_VDAC_DAC3_FILT_CTRL1 VPU_REG_ADDR(VENC_VDAC_DAC3_FILT_CTRL1)
#define P_ENCT_VIDEO_EN VPU_REG_ADDR(ENCT_VIDEO_EN)
#define P_ENCT_VIDEO_Y_SCL VPU_REG_ADDR(ENCT_VIDEO_Y_SCL)
#define P_ENCT_VIDEO_PB_SCL VPU_REG_ADDR(ENCT_VIDEO_PB_SCL)
#define P_ENCT_VIDEO_PR_SCL VPU_REG_ADDR(ENCT_VIDEO_PR_SCL)
#define P_ENCT_VIDEO_Y_OFFST VPU_REG_ADDR(ENCT_VIDEO_Y_OFFST)
#define P_ENCT_VIDEO_PB_OFFST VPU_REG_ADDR(ENCT_VIDEO_PB_OFFST)
#define P_ENCT_VIDEO_PR_OFFST VPU_REG_ADDR(ENCT_VIDEO_PR_OFFST)
#define P_ENCT_VIDEO_MODE VPU_REG_ADDR(ENCT_VIDEO_MODE)
#define P_ENCT_VIDEO_MODE_ADV VPU_REG_ADDR(ENCT_VIDEO_MODE_ADV)
#define P_ENCT_DBG_PX_RST VPU_REG_ADDR(ENCT_DBG_PX_RST)
#define P_ENCT_DBG_LN_RST VPU_REG_ADDR(ENCT_DBG_LN_RST)
#define P_ENCT_DBG_PX_INT VPU_REG_ADDR(ENCT_DBG_PX_INT)
#define P_ENCT_DBG_LN_INT VPU_REG_ADDR(ENCT_DBG_LN_INT)
#define P_ENCT_VIDEO_YFP1_HTIME VPU_REG_ADDR(ENCT_VIDEO_YFP1_HTIME)
#define P_ENCT_VIDEO_YFP2_HTIME VPU_REG_ADDR(ENCT_VIDEO_YFP2_HTIME)
#define P_ENCT_VIDEO_YC_DLY VPU_REG_ADDR(ENCT_VIDEO_YC_DLY)
#define P_ENCT_VIDEO_MAX_PXCNT VPU_REG_ADDR(ENCT_VIDEO_MAX_PXCNT)
#define P_ENCT_VIDEO_HAVON_END VPU_REG_ADDR(ENCT_VIDEO_HAVON_END)
#define P_ENCT_VIDEO_HAVON_BEGIN VPU_REG_ADDR(ENCT_VIDEO_HAVON_BEGIN)
#define P_ENCT_VIDEO_VAVON_ELINE VPU_REG_ADDR(ENCT_VIDEO_VAVON_ELINE)
#define P_ENCT_VIDEO_VAVON_BLINE VPU_REG_ADDR(ENCT_VIDEO_VAVON_BLINE)
#define P_ENCT_VIDEO_HSO_BEGIN VPU_REG_ADDR(ENCT_VIDEO_HSO_BEGIN)
#define P_ENCT_VIDEO_HSO_END VPU_REG_ADDR(ENCT_VIDEO_HSO_END)
#define P_ENCT_VIDEO_VSO_BEGIN VPU_REG_ADDR(ENCT_VIDEO_VSO_BEGIN)
#define P_ENCT_VIDEO_VSO_END VPU_REG_ADDR(ENCT_VIDEO_VSO_END)
#define P_ENCT_VIDEO_VSO_BLINE VPU_REG_ADDR(ENCT_VIDEO_VSO_BLINE)
#define P_ENCT_VIDEO_VSO_ELINE VPU_REG_ADDR(ENCT_VIDEO_VSO_ELINE)
#define P_ENCT_VIDEO_MAX_LNCNT VPU_REG_ADDR(ENCT_VIDEO_MAX_LNCNT)
#define P_ENCT_VIDEO_BLANKY_VAL VPU_REG_ADDR(ENCT_VIDEO_BLANKY_VAL)
#define P_ENCT_VIDEO_BLANKPB_VAL VPU_REG_ADDR(ENCT_VIDEO_BLANKPB_VAL)
#define P_ENCT_VIDEO_BLANKPR_VAL VPU_REG_ADDR(ENCT_VIDEO_BLANKPR_VAL)
#define P_ENCT_VIDEO_HOFFST VPU_REG_ADDR(ENCT_VIDEO_HOFFST)
#define P_ENCT_VIDEO_VOFFST VPU_REG_ADDR(ENCT_VIDEO_VOFFST)
#define P_ENCT_VIDEO_RGB_CTRL VPU_REG_ADDR(ENCT_VIDEO_RGB_CTRL)
#define P_ENCT_VIDEO_FILT_CTRL VPU_REG_ADDR(ENCT_VIDEO_FILT_CTRL)
#define P_ENCT_VIDEO_OFLD_VPEQ_OFST VPU_REG_ADDR(ENCT_VIDEO_OFLD_VPEQ_OFST)
#define P_ENCT_VIDEO_OFLD_VOAV_OFST VPU_REG_ADDR(ENCT_VIDEO_OFLD_VOAV_OFST)
#define P_ENCT_VIDEO_MATRIX_CB VPU_REG_ADDR(ENCT_VIDEO_MATRIX_CB)
#define P_ENCT_VIDEO_MATRIX_CR VPU_REG_ADDR(ENCT_VIDEO_MATRIX_CR)
#define P_ENCT_VIDEO_RGBIN_CTRL VPU_REG_ADDR(ENCT_VIDEO_RGBIN_CTRL)
#define P_ENCT_MAX_LINE_SWITCH_POINT VPU_REG_ADDR(ENCT_MAX_LINE_SWITCH_POINT)
#define P_ENCT_DACSEL_0 VPU_REG_ADDR(ENCT_DACSEL_0)
#define P_ENCT_DACSEL_1 VPU_REG_ADDR(ENCT_DACSEL_1)
#define P_ENCL_VFIFO2VD_CTL VPU_REG_ADDR(ENCL_VFIFO2VD_CTL)
#define P_ENCL_VFIFO2VD_PIXEL_START VPU_REG_ADDR(ENCL_VFIFO2VD_PIXEL_START)
#define P_ENCL_VFIFO2VD_PIXEL_END VPU_REG_ADDR(ENCL_VFIFO2VD_PIXEL_END)
#define P_ENCL_VFIFO2VD_LINE_TOP_START VPU_REG_ADDR(ENCL_VFIFO2VD_LINE_TOP_START)
#define P_ENCL_VFIFO2VD_LINE_TOP_END VPU_REG_ADDR(ENCL_VFIFO2VD_LINE_TOP_END)
#define P_ENCL_VFIFO2VD_LINE_BOT_START VPU_REG_ADDR(ENCL_VFIFO2VD_LINE_BOT_START)
#define P_ENCL_VFIFO2VD_LINE_BOT_END VPU_REG_ADDR(ENCL_VFIFO2VD_LINE_BOT_END)
#define P_ENCL_VFIFO2VD_CTL2 VPU_REG_ADDR(ENCL_VFIFO2VD_CTL2)
#define P_ENCL_TST_EN VPU_REG_ADDR(ENCL_TST_EN)
#define P_ENCL_TST_MDSEL VPU_REG_ADDR(ENCL_TST_MDSEL)
#define P_ENCL_TST_Y VPU_REG_ADDR(ENCL_TST_Y)
#define P_ENCL_TST_CB VPU_REG_ADDR(ENCL_TST_CB)
#define P_ENCL_TST_CR VPU_REG_ADDR(ENCL_TST_CR)
#define P_ENCL_TST_CLRBAR_STRT VPU_REG_ADDR(ENCL_TST_CLRBAR_STRT)
#define P_ENCL_TST_CLRBAR_WIDTH VPU_REG_ADDR(ENCL_TST_CLRBAR_WIDTH)
#define P_ENCL_TST_VDCNT_STSET VPU_REG_ADDR(ENCL_TST_VDCNT_STSET)
#define P_ENCL_VIDEO_EN VPU_REG_ADDR(ENCL_VIDEO_EN)
#define P_ENCL_VIDEO_Y_SCL VPU_REG_ADDR(ENCL_VIDEO_Y_SCL)
#define P_ENCL_VIDEO_PB_SCL VPU_REG_ADDR(ENCL_VIDEO_PB_SCL)
#define P_ENCL_VIDEO_PR_SCL VPU_REG_ADDR(ENCL_VIDEO_PR_SCL)
#define P_ENCL_VIDEO_Y_OFFST VPU_REG_ADDR(ENCL_VIDEO_Y_OFFST)
#define P_ENCL_VIDEO_PB_OFFST VPU_REG_ADDR(ENCL_VIDEO_PB_OFFST)
#define P_ENCL_VIDEO_PR_OFFST VPU_REG_ADDR(ENCL_VIDEO_PR_OFFST)
#define P_ENCL_VIDEO_MODE VPU_REG_ADDR(ENCL_VIDEO_MODE)
#define P_ENCL_VIDEO_MODE_ADV VPU_REG_ADDR(ENCL_VIDEO_MODE_ADV)
#define P_ENCL_DBG_PX_RST VPU_REG_ADDR(ENCL_DBG_PX_RST)
#define P_ENCL_DBG_LN_RST VPU_REG_ADDR(ENCL_DBG_LN_RST)
#define P_ENCL_DBG_PX_INT VPU_REG_ADDR(ENCL_DBG_PX_INT)
#define P_ENCL_DBG_LN_INT VPU_REG_ADDR(ENCL_DBG_LN_INT)
#define P_ENCL_VIDEO_YFP1_HTIME VPU_REG_ADDR(ENCL_VIDEO_YFP1_HTIME)
#define P_ENCL_VIDEO_YFP2_HTIME VPU_REG_ADDR(ENCL_VIDEO_YFP2_HTIME)
#define P_ENCL_VIDEO_YC_DLY VPU_REG_ADDR(ENCL_VIDEO_YC_DLY)
#define P_ENCL_VIDEO_MAX_PXCNT VPU_REG_ADDR(ENCL_VIDEO_MAX_PXCNT)
#define P_ENCL_VIDEO_HAVON_END VPU_REG_ADDR(ENCL_VIDEO_HAVON_END)
#define P_ENCL_VIDEO_HAVON_BEGIN VPU_REG_ADDR(ENCL_VIDEO_HAVON_BEGIN)
#define P_ENCL_VIDEO_VAVON_ELINE VPU_REG_ADDR(ENCL_VIDEO_VAVON_ELINE)
#define P_ENCL_VIDEO_VAVON_BLINE VPU_REG_ADDR(ENCL_VIDEO_VAVON_BLINE)
#define P_ENCL_VIDEO_HSO_BEGIN VPU_REG_ADDR(ENCL_VIDEO_HSO_BEGIN)
#define P_ENCL_VIDEO_HSO_END VPU_REG_ADDR(ENCL_VIDEO_HSO_END)
#define P_ENCL_VIDEO_VSO_BEGIN VPU_REG_ADDR(ENCL_VIDEO_VSO_BEGIN)
#define P_ENCL_VIDEO_VSO_END VPU_REG_ADDR(ENCL_VIDEO_VSO_END)
#define P_ENCL_VIDEO_VSO_BLINE VPU_REG_ADDR(ENCL_VIDEO_VSO_BLINE)
#define P_ENCL_VIDEO_VSO_ELINE VPU_REG_ADDR(ENCL_VIDEO_VSO_ELINE)
#define P_ENCL_VIDEO_MAX_LNCNT VPU_REG_ADDR(ENCL_VIDEO_MAX_LNCNT)
#define P_ENCL_VIDEO_BLANKY_VAL VPU_REG_ADDR(ENCL_VIDEO_BLANKY_VAL)
#define P_ENCL_VIDEO_BLANKPB_VAL VPU_REG_ADDR(ENCL_VIDEO_BLANKPB_VAL)
#define P_ENCL_VIDEO_BLANKPR_VAL VPU_REG_ADDR(ENCL_VIDEO_BLANKPR_VAL)
#define P_ENCL_VIDEO_HOFFST VPU_REG_ADDR(ENCL_VIDEO_HOFFST)
#define P_ENCL_VIDEO_VOFFST VPU_REG_ADDR(ENCL_VIDEO_VOFFST)
#define P_ENCL_VIDEO_RGB_CTRL VPU_REG_ADDR(ENCL_VIDEO_RGB_CTRL)
#define P_ENCL_VIDEO_FILT_CTRL VPU_REG_ADDR(ENCL_VIDEO_FILT_CTRL)
#define P_ENCL_VIDEO_OFLD_VPEQ_OFST VPU_REG_ADDR(ENCL_VIDEO_OFLD_VPEQ_OFST)
#define P_ENCL_VIDEO_OFLD_VOAV_OFST VPU_REG_ADDR(ENCL_VIDEO_OFLD_VOAV_OFST)
#define P_ENCL_VIDEO_MATRIX_CB VPU_REG_ADDR(ENCL_VIDEO_MATRIX_CB)
#define P_ENCL_VIDEO_MATRIX_CR VPU_REG_ADDR(ENCL_VIDEO_MATRIX_CR)
#define P_ENCL_VIDEO_RGBIN_CTRL VPU_REG_ADDR(ENCL_VIDEO_RGBIN_CTRL)
#define P_ENCL_MAX_LINE_SWITCH_POINT VPU_REG_ADDR(ENCL_MAX_LINE_SWITCH_POINT)
#define P_ENCL_DACSEL_0 VPU_REG_ADDR(ENCL_DACSEL_0)
#define P_ENCL_DACSEL_1 VPU_REG_ADDR(ENCL_DACSEL_1)
#define P_RDMA_AHB_START_ADDR_MAN VPU_REG_ADDR(RDMA_AHB_START_ADDR_MAN)
#define P_RDMA_AHB_END_ADDR_MAN VPU_REG_ADDR(RDMA_AHB_END_ADDR_MAN)
#define P_RDMA_AHB_START_ADDR_1 VPU_REG_ADDR(RDMA_AHB_START_ADDR_1)
#define P_RDMA_AHB_END_ADDR_1 VPU_REG_ADDR(RDMA_AHB_END_ADDR_1)
#define P_RDMA_AHB_START_ADDR_2 VPU_REG_ADDR(RDMA_AHB_START_ADDR_2)
#define P_RDMA_AHB_END_ADDR_2 VPU_REG_ADDR(RDMA_AHB_END_ADDR_2)
#define P_RDMA_AHB_START_ADDR_3 VPU_REG_ADDR(RDMA_AHB_START_ADDR_3)
#define P_RDMA_AHB_END_ADDR_3 VPU_REG_ADDR(RDMA_AHB_END_ADDR_3)
#define P_RDMA_ACCESS_AUTO VPU_REG_ADDR(RDMA_ACCESS_AUTO)
#define P_RDMA_ACCESS_MAN VPU_REG_ADDR(RDMA_ACCESS_MAN)
#define P_RDMA_CTRL VPU_REG_ADDR(RDMA_CTRL)
#define P_RDMA_STATUS VPU_REG_ADDR(RDMA_STATUS)
#define P_L_GAMMA_CNTL_PORT VPU_REG_ADDR(L_GAMMA_CNTL_PORT)
#define P_L_GAMMA_DATA_PORT VPU_REG_ADDR(L_GAMMA_DATA_PORT)
#define P_L_GAMMA_ADDR_PORT VPU_REG_ADDR(L_GAMMA_ADDR_PORT)
#define P_L_GAMMA_VCOM_HSWITCH_ADDR VPU_REG_ADDR(L_GAMMA_VCOM_HSWITCH_ADDR)
#define P_L_RGB_BASE_ADDR VPU_REG_ADDR(L_RGB_BASE_ADDR)
#define P_L_RGB_COEFF_ADDR VPU_REG_ADDR(L_RGB_COEFF_ADDR)
#define P_L_POL_CNTL_ADDR VPU_REG_ADDR(L_POL_CNTL_ADDR)
#define P_L_DITH_CNTL_ADDR VPU_REG_ADDR(L_DITH_CNTL_ADDR)
#define P_L_GAMMA_PROBE_CTRL VPU_REG_ADDR(L_GAMMA_PROBE_CTRL)
#define P_L_GAMMA_PROBE_COLOR_L VPU_REG_ADDR(L_GAMMA_PROBE_COLOR_L)
#define P_L_GAMMA_PROBE_COLOR_H VPU_REG_ADDR(L_GAMMA_PROBE_COLOR_H)
#define P_L_GAMMA_PROBE_HL_COLOR VPU_REG_ADDR(L_GAMMA_PROBE_HL_COLOR)
#define P_L_GAMMA_PROBE_POS_X VPU_REG_ADDR(L_GAMMA_PROBE_POS_X)
#define P_L_GAMMA_PROBE_POS_Y VPU_REG_ADDR(L_GAMMA_PROBE_POS_Y)
#define P_L_STH1_HS_ADDR VPU_REG_ADDR(L_STH1_HS_ADDR)
#define P_L_STH1_HE_ADDR VPU_REG_ADDR(L_STH1_HE_ADDR)
#define P_L_STH1_VS_ADDR VPU_REG_ADDR(L_STH1_VS_ADDR)
#define P_L_STH1_VE_ADDR VPU_REG_ADDR(L_STH1_VE_ADDR)
#define P_L_STH2_HS_ADDR VPU_REG_ADDR(L_STH2_HS_ADDR)
#define P_L_STH2_HE_ADDR VPU_REG_ADDR(L_STH2_HE_ADDR)
#define P_L_STH2_VS_ADDR VPU_REG_ADDR(L_STH2_VS_ADDR)
#define P_L_STH2_VE_ADDR VPU_REG_ADDR(L_STH2_VE_ADDR)
#define P_L_OEH_HS_ADDR VPU_REG_ADDR(L_OEH_HS_ADDR)
#define P_L_OEH_HE_ADDR VPU_REG_ADDR(L_OEH_HE_ADDR)
#define P_L_OEH_VS_ADDR VPU_REG_ADDR(L_OEH_VS_ADDR)
#define P_L_OEH_VE_ADDR VPU_REG_ADDR(L_OEH_VE_ADDR)
#define P_L_VCOM_HSWITCH_ADDR VPU_REG_ADDR(L_VCOM_HSWITCH_ADDR)
#define P_L_VCOM_VS_ADDR VPU_REG_ADDR(L_VCOM_VS_ADDR)
#define P_L_VCOM_VE_ADDR VPU_REG_ADDR(L_VCOM_VE_ADDR)
#define P_L_CPV1_HS_ADDR VPU_REG_ADDR(L_CPV1_HS_ADDR)
#define P_L_CPV1_HE_ADDR VPU_REG_ADDR(L_CPV1_HE_ADDR)
#define P_L_CPV1_VS_ADDR VPU_REG_ADDR(L_CPV1_VS_ADDR)
#define P_L_CPV1_VE_ADDR VPU_REG_ADDR(L_CPV1_VE_ADDR)
#define P_L_CPV2_HS_ADDR VPU_REG_ADDR(L_CPV2_HS_ADDR)
#define P_L_CPV2_HE_ADDR VPU_REG_ADDR(L_CPV2_HE_ADDR)
#define P_L_CPV2_VS_ADDR VPU_REG_ADDR(L_CPV2_VS_ADDR)
#define P_L_CPV2_VE_ADDR VPU_REG_ADDR(L_CPV2_VE_ADDR)
#define P_L_STV1_HS_ADDR VPU_REG_ADDR(L_STV1_HS_ADDR)
#define P_L_STV1_HE_ADDR VPU_REG_ADDR(L_STV1_HE_ADDR)
#define P_L_STV1_VS_ADDR VPU_REG_ADDR(L_STV1_VS_ADDR)
#define P_L_STV1_VE_ADDR VPU_REG_ADDR(L_STV1_VE_ADDR)
#define P_L_STV2_HS_ADDR VPU_REG_ADDR(L_STV2_HS_ADDR)
#define P_L_STV2_HE_ADDR VPU_REG_ADDR(L_STV2_HE_ADDR)
#define P_L_STV2_VS_ADDR VPU_REG_ADDR(L_STV2_VS_ADDR)
#define P_L_STV2_VE_ADDR VPU_REG_ADDR(L_STV2_VE_ADDR)
#define P_L_OEV1_HS_ADDR VPU_REG_ADDR(L_OEV1_HS_ADDR)
#define P_L_OEV1_HE_ADDR VPU_REG_ADDR(L_OEV1_HE_ADDR)
#define P_L_OEV1_VS_ADDR VPU_REG_ADDR(L_OEV1_VS_ADDR)
#define P_L_OEV1_VE_ADDR VPU_REG_ADDR(L_OEV1_VE_ADDR)
#define P_L_OEV2_HS_ADDR VPU_REG_ADDR(L_OEV2_HS_ADDR)
#define P_L_OEV2_HE_ADDR VPU_REG_ADDR(L_OEV2_HE_ADDR)
#define P_L_OEV2_VS_ADDR VPU_REG_ADDR(L_OEV2_VS_ADDR)
#define P_L_OEV2_VE_ADDR VPU_REG_ADDR(L_OEV2_VE_ADDR)
#define P_L_OEV3_HS_ADDR VPU_REG_ADDR(L_OEV3_HS_ADDR)
#define P_L_OEV3_HE_ADDR VPU_REG_ADDR(L_OEV3_HE_ADDR)
#define P_L_OEV3_VS_ADDR VPU_REG_ADDR(L_OEV3_VS_ADDR)
#define P_L_OEV3_VE_ADDR VPU_REG_ADDR(L_OEV3_VE_ADDR)
#define P_L_LCD_PWR_ADDR VPU_REG_ADDR(L_LCD_PWR_ADDR)
#define P_L_LCD_PWM0_LO_ADDR VPU_REG_ADDR(L_LCD_PWM0_LO_ADDR)
#define P_L_LCD_PWM0_HI_ADDR VPU_REG_ADDR(L_LCD_PWM0_HI_ADDR)
#define P_L_LCD_PWM1_LO_ADDR VPU_REG_ADDR(L_LCD_PWM1_LO_ADDR)
#define P_L_LCD_PWM1_HI_ADDR VPU_REG_ADDR(L_LCD_PWM1_HI_ADDR)
#define P_L_INV_CNT_ADDR VPU_REG_ADDR(L_INV_CNT_ADDR)
#define P_L_TCON_MISC_SEL_ADDR VPU_REG_ADDR(L_TCON_MISC_SEL_ADDR)
#define P_L_DUAL_PORT_CNTL_ADDR VPU_REG_ADDR(L_DUAL_PORT_CNTL_ADDR)
#define P_MLVDS_CLK_CTL1_HI VPU_REG_ADDR(MLVDS_CLK_CTL1_HI)
#define P_MLVDS_CLK_CTL1_LO VPU_REG_ADDR(MLVDS_CLK_CTL1_LO)
#define P_L_TCON_DOUBLE_CTL VPU_REG_ADDR(L_TCON_DOUBLE_CTL)
#define P_L_TCON_PATTERN_HI VPU_REG_ADDR(L_TCON_PATTERN_HI)
#define P_L_TCON_PATTERN_LO VPU_REG_ADDR(L_TCON_PATTERN_LO)
#define P_LDIM_BL_ADDR_PORT VPU_REG_ADDR(LDIM_BL_ADDR_PORT)
#define P_LDIM_BL_DATA_PORT VPU_REG_ADDR(LDIM_BL_DATA_PORT)
#define P_L_DE_HS_ADDR VPU_REG_ADDR(L_DE_HS_ADDR)
#define P_L_DE_HE_ADDR VPU_REG_ADDR(L_DE_HE_ADDR)
#define P_L_DE_VS_ADDR VPU_REG_ADDR(L_DE_VS_ADDR)
#define P_L_DE_VE_ADDR VPU_REG_ADDR(L_DE_VE_ADDR)
#define P_L_HSYNC_HS_ADDR VPU_REG_ADDR(L_HSYNC_HS_ADDR)
#define P_L_HSYNC_HE_ADDR VPU_REG_ADDR(L_HSYNC_HE_ADDR)
#define P_L_HSYNC_VS_ADDR VPU_REG_ADDR(L_HSYNC_VS_ADDR)
#define P_L_HSYNC_VE_ADDR VPU_REG_ADDR(L_HSYNC_VE_ADDR)
#define P_L_VSYNC_HS_ADDR VPU_REG_ADDR(L_VSYNC_HS_ADDR)
#define P_L_VSYNC_HE_ADDR VPU_REG_ADDR(L_VSYNC_HE_ADDR)
#define P_L_VSYNC_VS_ADDR VPU_REG_ADDR(L_VSYNC_VS_ADDR)
#define P_L_VSYNC_VE_ADDR VPU_REG_ADDR(L_VSYNC_VE_ADDR)
#define P_L_LCD_MCU_CTL VPU_REG_ADDR(L_LCD_MCU_CTL)
#define P_DUAL_MLVDS_CTL VPU_REG_ADDR(DUAL_MLVDS_CTL)
#define P_DUAL_MLVDS_LINE_START VPU_REG_ADDR(DUAL_MLVDS_LINE_START)
#define P_DUAL_MLVDS_LINE_END VPU_REG_ADDR(DUAL_MLVDS_LINE_END)
#define P_DUAL_MLVDS_PIXEL_W_START_L VPU_REG_ADDR(DUAL_MLVDS_PIXEL_W_START_L)
#define P_DUAL_MLVDS_PIXEL_W_END_L VPU_REG_ADDR(DUAL_MLVDS_PIXEL_W_END_L)
#define P_DUAL_MLVDS_PIXEL_W_START_R VPU_REG_ADDR(DUAL_MLVDS_PIXEL_W_START_R)
#define P_DUAL_MLVDS_PIXEL_W_END_R VPU_REG_ADDR(DUAL_MLVDS_PIXEL_W_END_R)
#define P_DUAL_MLVDS_PIXEL_R_START_L VPU_REG_ADDR(DUAL_MLVDS_PIXEL_R_START_L)
#define P_DUAL_MLVDS_PIXEL_R_CNT_L VPU_REG_ADDR(DUAL_MLVDS_PIXEL_R_CNT_L)
#define P_DUAL_MLVDS_PIXEL_R_START_R VPU_REG_ADDR(DUAL_MLVDS_PIXEL_R_START_R)
#define P_DUAL_MLVDS_PIXEL_R_CNT_R VPU_REG_ADDR(DUAL_MLVDS_PIXEL_R_CNT_R)
#define P_V_INVERSION_PIXEL VPU_REG_ADDR(V_INVERSION_PIXEL)
#define P_V_INVERSION_LINE VPU_REG_ADDR(V_INVERSION_LINE)
#define P_V_INVERSION_CONTROL VPU_REG_ADDR(V_INVERSION_CONTROL)
#define P_MLVDS2_CONTROL VPU_REG_ADDR(MLVDS2_CONTROL)
#define P_MLVDS2_CONFIG_HI VPU_REG_ADDR(MLVDS2_CONFIG_HI)
#define P_MLVDS2_CONFIG_LO VPU_REG_ADDR(MLVDS2_CONFIG_LO)
#define P_MLVDS2_DUAL_GATE_WR_START VPU_REG_ADDR(MLVDS2_DUAL_GATE_WR_START)
#define P_MLVDS2_DUAL_GATE_WR_END VPU_REG_ADDR(MLVDS2_DUAL_GATE_WR_END)
#define P_MLVDS2_DUAL_GATE_RD_START VPU_REG_ADDR(MLVDS2_DUAL_GATE_RD_START)
#define P_MLVDS2_DUAL_GATE_RD_END VPU_REG_ADDR(MLVDS2_DUAL_GATE_RD_END)
#define P_MLVDS2_SECOND_RESET_CTL VPU_REG_ADDR(MLVDS2_SECOND_RESET_CTL)
#define P_MLVDS2_DUAL_GATE_CTL_HI VPU_REG_ADDR(MLVDS2_DUAL_GATE_CTL_HI)
#define P_MLVDS2_DUAL_GATE_CTL_LO VPU_REG_ADDR(MLVDS2_DUAL_GATE_CTL_LO)
#define P_MLVDS2_RESET_CONFIG_HI VPU_REG_ADDR(MLVDS2_RESET_CONFIG_HI)
#define P_MLVDS2_RESET_CONFIG_LO VPU_REG_ADDR(MLVDS2_RESET_CONFIG_LO)
#define P_GAMMA_CNTL_PORT VPU_REG_ADDR(GAMMA_CNTL_PORT)
#define P_GAMMA_DATA_PORT VPU_REG_ADDR(GAMMA_DATA_PORT)
#define P_GAMMA_ADDR_PORT VPU_REG_ADDR(GAMMA_ADDR_PORT)
#define P_GAMMA_VCOM_HSWITCH_ADDR VPU_REG_ADDR(GAMMA_VCOM_HSWITCH_ADDR)
#define P_RGB_BASE_ADDR VPU_REG_ADDR(RGB_BASE_ADDR)
#define P_RGB_COEFF_ADDR VPU_REG_ADDR(RGB_COEFF_ADDR)
#define P_POL_CNTL_ADDR VPU_REG_ADDR(POL_CNTL_ADDR)
#define P_DITH_CNTL_ADDR VPU_REG_ADDR(DITH_CNTL_ADDR)
#define P_GAMMA_PROBE_CTRL VPU_REG_ADDR(GAMMA_PROBE_CTRL)
#define P_GAMMA_PROBE_COLOR_L VPU_REG_ADDR(GAMMA_PROBE_COLOR_L)
#define P_GAMMA_PROBE_COLOR_H VPU_REG_ADDR(GAMMA_PROBE_COLOR_H)
#define P_GAMMA_PROBE_HL_COLOR VPU_REG_ADDR(GAMMA_PROBE_HL_COLOR)
#define P_GAMMA_PROBE_POS_X VPU_REG_ADDR(GAMMA_PROBE_POS_X)
#define P_GAMMA_PROBE_POS_Y VPU_REG_ADDR(GAMMA_PROBE_POS_Y)
#define P_STH1_HS_ADDR VPU_REG_ADDR(STH1_HS_ADDR)
#define P_STH1_HE_ADDR VPU_REG_ADDR(STH1_HE_ADDR)
#define P_STH1_VS_ADDR VPU_REG_ADDR(STH1_VS_ADDR)
#define P_STH1_VE_ADDR VPU_REG_ADDR(STH1_VE_ADDR)
#define P_STH2_HS_ADDR VPU_REG_ADDR(STH2_HS_ADDR)
#define P_STH2_HE_ADDR VPU_REG_ADDR(STH2_HE_ADDR)
#define P_STH2_VS_ADDR VPU_REG_ADDR(STH2_VS_ADDR)
#define P_STH2_VE_ADDR VPU_REG_ADDR(STH2_VE_ADDR)
#define P_OEH_HS_ADDR VPU_REG_ADDR(OEH_HS_ADDR)
#define P_OEH_HE_ADDR VPU_REG_ADDR(OEH_HE_ADDR)
#define P_OEH_VS_ADDR VPU_REG_ADDR(OEH_VS_ADDR)
#define P_OEH_VE_ADDR VPU_REG_ADDR(OEH_VE_ADDR)
#define P_VCOM_HSWITCH_ADDR VPU_REG_ADDR(VCOM_HSWITCH_ADDR)
#define P_VCOM_VS_ADDR VPU_REG_ADDR(VCOM_VS_ADDR)
#define P_VCOM_VE_ADDR VPU_REG_ADDR(VCOM_VE_ADDR)
#define P_CPV1_HS_ADDR VPU_REG_ADDR(CPV1_HS_ADDR)
#define P_CPV1_HE_ADDR VPU_REG_ADDR(CPV1_HE_ADDR)
#define P_CPV1_VS_ADDR VPU_REG_ADDR(CPV1_VS_ADDR)
#define P_CPV1_VE_ADDR VPU_REG_ADDR(CPV1_VE_ADDR)
#define P_CPV2_HS_ADDR VPU_REG_ADDR(CPV2_HS_ADDR)
#define P_CPV2_HE_ADDR VPU_REG_ADDR(CPV2_HE_ADDR)
#define P_CPV2_VS_ADDR VPU_REG_ADDR(CPV2_VS_ADDR)
#define P_CPV2_VE_ADDR VPU_REG_ADDR(CPV2_VE_ADDR)
#define P_STV1_HS_ADDR VPU_REG_ADDR(STV1_HS_ADDR)
#define P_STV1_HE_ADDR VPU_REG_ADDR(STV1_HE_ADDR)
#define P_STV1_VS_ADDR VPU_REG_ADDR(STV1_VS_ADDR)
#define P_STV1_VE_ADDR VPU_REG_ADDR(STV1_VE_ADDR)
#define P_STV2_HS_ADDR VPU_REG_ADDR(STV2_HS_ADDR)
#define P_STV2_HE_ADDR VPU_REG_ADDR(STV2_HE_ADDR)
#define P_STV2_VS_ADDR VPU_REG_ADDR(STV2_VS_ADDR)
#define P_STV2_VE_ADDR VPU_REG_ADDR(STV2_VE_ADDR)
#define P_OEV1_HS_ADDR VPU_REG_ADDR(OEV1_HS_ADDR)
#define P_OEV1_HE_ADDR VPU_REG_ADDR(OEV1_HE_ADDR)
#define P_OEV1_VS_ADDR VPU_REG_ADDR(OEV1_VS_ADDR)
#define P_OEV1_VE_ADDR VPU_REG_ADDR(OEV1_VE_ADDR)
#define P_OEV2_HS_ADDR VPU_REG_ADDR(OEV2_HS_ADDR)
#define P_OEV2_HE_ADDR VPU_REG_ADDR(OEV2_HE_ADDR)
#define P_OEV2_VS_ADDR VPU_REG_ADDR(OEV2_VS_ADDR)
#define P_OEV2_VE_ADDR VPU_REG_ADDR(OEV2_VE_ADDR)
#define P_OEV3_HS_ADDR VPU_REG_ADDR(OEV3_HS_ADDR)
#define P_OEV3_HE_ADDR VPU_REG_ADDR(OEV3_HE_ADDR)
#define P_OEV3_VS_ADDR VPU_REG_ADDR(OEV3_VS_ADDR)
#define P_OEV3_VE_ADDR VPU_REG_ADDR(OEV3_VE_ADDR)
#define P_LCD_PWR_ADDR VPU_REG_ADDR(LCD_PWR_ADDR)
#define P_LCD_PWM0_LO_ADDR VPU_REG_ADDR(LCD_PWM0_LO_ADDR)
#define P_LCD_PWM0_HI_ADDR VPU_REG_ADDR(LCD_PWM0_HI_ADDR)
#define P_LCD_PWM1_LO_ADDR VPU_REG_ADDR(LCD_PWM1_LO_ADDR)
#define P_LCD_PWM1_HI_ADDR VPU_REG_ADDR(LCD_PWM1_HI_ADDR)
#define P_INV_CNT_ADDR VPU_REG_ADDR(INV_CNT_ADDR)
#define P_TCON_MISC_SEL_ADDR VPU_REG_ADDR(TCON_MISC_SEL_ADDR)
#define P_DUAL_PORT_CNTL_ADDR VPU_REG_ADDR(DUAL_PORT_CNTL_ADDR)
#define P_MLVDS_CONTROL VPU_REG_ADDR(MLVDS_CONTROL)
#define P_MLVDS_RESET_PATTERN_HI VPU_REG_ADDR(MLVDS_RESET_PATTERN_HI)
#define P_MLVDS_RESET_PATTERN_LO VPU_REG_ADDR(MLVDS_RESET_PATTERN_LO)
#define P_MLVDS_RESET_PATTERN_EXT VPU_REG_ADDR(MLVDS_RESET_PATTERN_EXT)
#define P_MLVDS_CONFIG_HI VPU_REG_ADDR(MLVDS_CONFIG_HI)
#define P_MLVDS_CONFIG_LO VPU_REG_ADDR(MLVDS_CONFIG_LO)
#define P_TCON_DOUBLE_CTL VPU_REG_ADDR(TCON_DOUBLE_CTL)
#define P_TCON_PATTERN_HI VPU_REG_ADDR(TCON_PATTERN_HI)
#define P_TCON_PATTERN_LO VPU_REG_ADDR(TCON_PATTERN_LO)
#define P_TCON_CONTROL_HI VPU_REG_ADDR(TCON_CONTROL_HI)
#define P_TCON_CONTROL_LO VPU_REG_ADDR(TCON_CONTROL_LO)
#define P_LVDS_BLANK_DATA_HI VPU_REG_ADDR(LVDS_BLANK_DATA_HI)
#define P_LVDS_BLANK_DATA_LO VPU_REG_ADDR(LVDS_BLANK_DATA_LO)
#define P_LVDS_PACK_CNTL_ADDR VPU_REG_ADDR(LVDS_PACK_CNTL_ADDR)
#define P_DE_HS_ADDR VPU_REG_ADDR(DE_HS_ADDR)
#define P_DE_HE_ADDR VPU_REG_ADDR(DE_HE_ADDR)
#define P_DE_VS_ADDR VPU_REG_ADDR(DE_VS_ADDR)
#define P_DE_VE_ADDR VPU_REG_ADDR(DE_VE_ADDR)
#define P_HSYNC_HS_ADDR VPU_REG_ADDR(HSYNC_HS_ADDR)
#define P_HSYNC_HE_ADDR VPU_REG_ADDR(HSYNC_HE_ADDR)
#define P_HSYNC_VS_ADDR VPU_REG_ADDR(HSYNC_VS_ADDR)
#define P_HSYNC_VE_ADDR VPU_REG_ADDR(HSYNC_VE_ADDR)
#define P_VSYNC_HS_ADDR VPU_REG_ADDR(VSYNC_HS_ADDR)
#define P_VSYNC_HE_ADDR VPU_REG_ADDR(VSYNC_HE_ADDR)
#define P_VSYNC_VS_ADDR VPU_REG_ADDR(VSYNC_VS_ADDR)
#define P_VSYNC_VE_ADDR VPU_REG_ADDR(VSYNC_VE_ADDR)
#define P_LCD_MCU_CTL VPU_REG_ADDR(LCD_MCU_CTL)
#define P_LCD_MCU_DATA_0 VPU_REG_ADDR(LCD_MCU_DATA_0)
#define P_LCD_MCU_DATA_1 VPU_REG_ADDR(LCD_MCU_DATA_1)
#define P_LVDS_GEN_CNTL VPU_REG_ADDR(LVDS_GEN_CNTL)
#define P_LVDS_PHY_CNTL0 VPU_REG_ADDR(LVDS_PHY_CNTL0)
#define P_LVDS_PHY_CNTL1 VPU_REG_ADDR(LVDS_PHY_CNTL1)
#define P_LVDS_PHY_CNTL2 VPU_REG_ADDR(LVDS_PHY_CNTL2)
#define P_LVDS_PHY_CNTL3 VPU_REG_ADDR(LVDS_PHY_CNTL3)
#define P_LVDS_PHY_CNTL4 VPU_REG_ADDR(LVDS_PHY_CNTL4)
#define P_LVDS_PHY_CNTL5 VPU_REG_ADDR(LVDS_PHY_CNTL5)
#define P_LVDS_SRG_TEST VPU_REG_ADDR(LVDS_SRG_TEST)
#define P_LVDS_BIST_MUX0 VPU_REG_ADDR(LVDS_BIST_MUX0)
#define P_LVDS_BIST_MUX1 VPU_REG_ADDR(LVDS_BIST_MUX1)
#define P_LVDS_BIST_FIXED0 VPU_REG_ADDR(LVDS_BIST_FIXED0)
#define P_LVDS_BIST_FIXED1 VPU_REG_ADDR(LVDS_BIST_FIXED1)
#define P_LVDS_BIST_CNTL0 VPU_REG_ADDR(LVDS_BIST_CNTL0)
#define P_LVDS_CLKB_CLKA VPU_REG_ADDR(LVDS_CLKB_CLKA)
#define P_LVDS_PHY_CLK_CNTL VPU_REG_ADDR(LVDS_PHY_CLK_CNTL)
#define P_LVDS_SER_EN VPU_REG_ADDR(LVDS_SER_EN)
#define P_LVDS_PHY_CNTL6 VPU_REG_ADDR(LVDS_PHY_CNTL6)
#define P_LVDS_PHY_CNTL7 VPU_REG_ADDR(LVDS_PHY_CNTL7)
#define P_LVDS_PHY_CNTL8 VPU_REG_ADDR(LVDS_PHY_CNTL8)
#define P_MLVDS_CLK_CTL0_HI VPU_REG_ADDR(MLVDS_CLK_CTL0_HI)
#define P_MLVDS_CLK_CTL0_LO VPU_REG_ADDR(MLVDS_CLK_CTL0_LO)
#define P_MLVDS_DUAL_GATE_WR_START VPU_REG_ADDR(MLVDS_DUAL_GATE_WR_START)
#define P_MLVDS_DUAL_GATE_WR_END VPU_REG_ADDR(MLVDS_DUAL_GATE_WR_END)
#define P_MLVDS_DUAL_GATE_RD_START VPU_REG_ADDR(MLVDS_DUAL_GATE_RD_START)
#define P_MLVDS_DUAL_GATE_RD_END VPU_REG_ADDR(MLVDS_DUAL_GATE_RD_END)
#define P_MLVDS_SECOND_RESET_CTL VPU_REG_ADDR(MLVDS_SECOND_RESET_CTL)
#define P_MLVDS_DUAL_GATE_CTL_HI VPU_REG_ADDR(MLVDS_DUAL_GATE_CTL_HI)
#define P_MLVDS_DUAL_GATE_CTL_LO VPU_REG_ADDR(MLVDS_DUAL_GATE_CTL_LO)
#define P_MLVDS_RESET_CONFIG_HI VPU_REG_ADDR(MLVDS_RESET_CONFIG_HI)
#define P_MLVDS_RESET_CONFIG_LO VPU_REG_ADDR(MLVDS_RESET_CONFIG_LO)
#define P_VPU_OSD1_MMC_CTRL VPU_REG_ADDR(VPU_OSD1_MMC_CTRL)
#define P_VPU_OSD2_MMC_CTRL VPU_REG_ADDR(VPU_OSD2_MMC_CTRL)
#define P_VPU_VD1_MMC_CTRL VPU_REG_ADDR(VPU_VD1_MMC_CTRL)
#define P_VPU_VD2_MMC_CTRL VPU_REG_ADDR(VPU_VD2_MMC_CTRL)
#define P_VPU_DI_IF1_MMC_CTRL VPU_REG_ADDR(VPU_DI_IF1_MMC_CTRL)
#define P_VPU_DI_MEM_MMC_CTRL VPU_REG_ADDR(VPU_DI_MEM_MMC_CTRL)
#define P_VPU_DI_INP_MMC_CTRL VPU_REG_ADDR(VPU_DI_INP_MMC_CTRL)
#define P_VPU_DI_MTNRD_MMC_CTRL VPU_REG_ADDR(VPU_DI_MTNRD_MMC_CTRL)
#define P_VPU_DI_CHAN2_MMC_CTRL VPU_REG_ADDR(VPU_DI_CHAN2_MMC_CTRL)
#define P_VPU_DI_MTNWR_MMC_CTRL VPU_REG_ADDR(VPU_DI_MTNWR_MMC_CTRL)
#define P_VPU_DI_NRWR_MMC_CTRL VPU_REG_ADDR(VPU_DI_NRWR_MMC_CTRL)
#define P_VPU_DI_DIWR_MMC_CTRL VPU_REG_ADDR(VPU_DI_DIWR_MMC_CTRL)
#define P_VPU_VDIN0_MMC_CTRL VPU_REG_ADDR(VPU_VDIN0_MMC_CTRL)
#define P_VPU_VDIN1_MMC_CTRL VPU_REG_ADDR(VPU_VDIN1_MMC_CTRL)
#define P_VPU_BT656_MMC_CTRL VPU_REG_ADDR(VPU_BT656_MMC_CTRL)
#define P_VPU_TVD3D_MMC_CTRL VPU_REG_ADDR(VPU_TVD3D_MMC_CTRL)
#define P_VPU_TVDVBI_MMC_CTRL VPU_REG_ADDR(VPU_TVDVBI_MMC_CTRL)
#define P_VPU_TVDVBI_VSLATCH_ADDR VPU_REG_ADDR(VPU_TVDVBI_VSLATCH_ADDR)
#define P_VPU_TVDVBI_WRRSP_ADDR VPU_REG_ADDR(VPU_TVDVBI_WRRSP_ADDR)
#define P_VPU_VDIN_PRE_ARB_CTRL VPU_REG_ADDR(VPU_VDIN_PRE_ARB_CTRL)
#define P_VPU_VDISP_PRE_ARB_CTRL VPU_REG_ADDR(VPU_VDISP_PRE_ARB_CTRL)
#define P_VPU_VPUARB2_PRE_ARB_CTRL VPU_REG_ADDR(VPU_VPUARB2_PRE_ARB_CTRL)
#define P_VPU_OSD3_MMC_CTRL VPU_REG_ADDR(VPU_OSD3_MMC_CTRL)
#define P_VPU_OSD4_MMC_CTRL VPU_REG_ADDR(VPU_OSD4_MMC_CTRL)
#define P_VPU_VD3_MMC_CTRL VPU_REG_ADDR(VPU_VD3_MMC_CTRL)
#define P_VPU_VIU_VENC_MUX_CTRL VPU_REG_ADDR(VPU_VIU_VENC_MUX_CTRL)
#define P_VPU_HDMI_SETTING VPU_REG_ADDR(VPU_HDMI_SETTING)
#define P_ENCI_INFO_READ VPU_REG_ADDR(ENCI_INFO_READ)
#define P_ENCP_INFO_READ VPU_REG_ADDR(ENCP_INFO_READ)
#define P_ENCT_INFO_READ VPU_REG_ADDR(ENCT_INFO_READ)
#define P_ENCL_INFO_READ VPU_REG_ADDR(ENCL_INFO_READ)
#define P_VPU_SW_RESET VPU_REG_ADDR(VPU_SW_RESET)
#define P_VPU_D2D3_MMC_CTRL VPU_REG_ADDR(VPU_D2D3_MMC_CTRL)
#define P_VPU_CONT_MMC_CTRL VPU_REG_ADDR(VPU_CONT_MMC_CTRL)
#define P_VPU_CLK_GATE VPU_REG_ADDR(VPU_CLK_GATE)
#define P_VPU_RDMA_MMC_CTRL VPU_REG_ADDR(VPU_RDMA_MMC_CTRL)
#define P_VPU_MEM_PD_REG0 VPU_REG_ADDR(VPU_MEM_PD_REG0)
#define P_VPU_MEM_PD_REG1 VPU_REG_ADDR(VPU_MEM_PD_REG1)
#define P_VPU_HDMI_DATA_OVR VPU_REG_ADDR(VPU_HDMI_DATA_OVR)
#define P_VPU_PROT1_MMC_CTRL VPU_REG_ADDR(VPU_PROT1_MMC_CTRL)
#define P_VPU_PROT2_MMC_CTRL VPU_REG_ADDR(VPU_PROT2_MMC_CTRL)
#define P_VPU_PROT3_MMC_CTRL VPU_REG_ADDR(VPU_PROT3_MMC_CTRL)
#define P_VPU_ARB4_V1_MMC_CTRL VPU_REG_ADDR(VPU_ARB4_V1_MMC_CTRL)
#define P_VPU_ARB4_V2_MMC_CTRL VPU_REG_ADDR(VPU_ARB4_V2_MMC_CTRL)
#define P_VPU_VPU_PWM_V0 VPU_REG_ADDR(VPU_VPU_PWM_V0)
#define P_VPU_VPU_PWM_V1 VPU_REG_ADDR(VPU_VPU_PWM_V1)
#define P_VPU_VPU_PWM_V2 VPU_REG_ADDR(VPU_VPU_PWM_V2)
#define P_VPU_VPU_PWM_V3 VPU_REG_ADDR(VPU_VPU_PWM_V3)
#define P_VPU_VPU_PWM_H0 VPU_REG_ADDR(VPU_VPU_PWM_H0)
#define P_VPU_VPU_PWM_H1 VPU_REG_ADDR(VPU_VPU_PWM_H1)
#define P_VPU_VPU_PWM_H2 VPU_REG_ADDR(VPU_VPU_PWM_H2)
#define P_VPU_VPU_PWM_H3 VPU_REG_ADDR(VPU_VPU_PWM_H3)
#define P_VPU_MISC_CTRL VPU_REG_ADDR(VPU_MISC_CTRL)
#define P_VPU_ISP_GCLK_CTRL0 VPU_REG_ADDR(VPU_ISP_GCLK_CTRL0)
#define P_VPU_ISP_GCLK_CTRL1 VPU_REG_ADDR(VPU_ISP_GCLK_CTRL1)
#define P_VPU_PROT1_CLK_GATE VPU_REG_ADDR(VPU_PROT1_CLK_GATE)
#define P_VPU_PROT1_GEN_CNTL VPU_REG_ADDR(VPU_PROT1_GEN_CNTL)
#define P_VPU_PROT1_X_START_END VPU_REG_ADDR(VPU_PROT1_X_START_END)
#define P_VPU_PROT1_Y_START_END VPU_REG_ADDR(VPU_PROT1_Y_START_END)
#define P_VPU_PROT1_Y_LEN_STEP VPU_REG_ADDR(VPU_PROT1_Y_LEN_STEP)
#define P_VPU_PROT1_RPT_LOOP VPU_REG_ADDR(VPU_PROT1_RPT_LOOP)
#define P_VPU_PROT1_RPT_PAT VPU_REG_ADDR(VPU_PROT1_RPT_PAT)
#define P_VPU_PROT1_DDR VPU_REG_ADDR(VPU_PROT1_DDR)
#define P_VPU_PROT1_RBUF_ROOM VPU_REG_ADDR(VPU_PROT1_RBUF_ROOM)
#define P_VPU_PROT1_STAT_0 VPU_REG_ADDR(VPU_PROT1_STAT_0)
#define P_VPU_PROT1_STAT_1 VPU_REG_ADDR(VPU_PROT1_STAT_1)
#define P_VPU_PROT1_STAT_2 VPU_REG_ADDR(VPU_PROT1_STAT_2)
#define P_VPU_PROT1_REQ_ONOFF VPU_REG_ADDR(VPU_PROT1_REQ_ONOFF)
#define P_VPU_PROT2_CLK_GATE VPU_REG_ADDR(VPU_PROT2_CLK_GATE)
#define P_VPU_PROT2_GEN_CNTL VPU_REG_ADDR(VPU_PROT2_GEN_CNTL)
#define P_VPU_PROT2_X_START_END VPU_REG_ADDR(VPU_PROT2_X_START_END)
#define P_VPU_PROT2_Y_START_END VPU_REG_ADDR(VPU_PROT2_Y_START_END)
#define P_VPU_PROT2_Y_LEN_STEP VPU_REG_ADDR(VPU_PROT2_Y_LEN_STEP)
#define P_VPU_PROT2_RPT_LOOP VPU_REG_ADDR(VPU_PROT2_RPT_LOOP)
#define P_VPU_PROT2_RPT_PAT VPU_REG_ADDR(VPU_PROT2_RPT_PAT)
#define P_VPU_PROT2_DDR VPU_REG_ADDR(VPU_PROT2_DDR)
#define P_VPU_PROT2_RBUF_ROOM VPU_REG_ADDR(VPU_PROT2_RBUF_ROOM)
#define P_VPU_PROT2_STAT_0 VPU_REG_ADDR(VPU_PROT2_STAT_0)
#define P_VPU_PROT2_STAT_1 VPU_REG_ADDR(VPU_PROT2_STAT_1)
#define P_VPU_PROT2_STAT_2 VPU_REG_ADDR(VPU_PROT2_STAT_2)
#define P_VPU_PROT2_REQ_ONOFF VPU_REG_ADDR(VPU_PROT2_REQ_ONOFF)
#define P_VPU_PROT3_CLK_GATE VPU_REG_ADDR(VPU_PROT3_CLK_GATE)
#define P_VPU_PROT3_GEN_CNTL VPU_REG_ADDR(VPU_PROT3_GEN_CNTL)
#define P_VPU_PROT3_X_START_END VPU_REG_ADDR(VPU_PROT3_X_START_END)
#define P_VPU_PROT3_Y_START_END VPU_REG_ADDR(VPU_PROT3_Y_START_END)
#define P_VPU_PROT3_Y_LEN_STEP VPU_REG_ADDR(VPU_PROT3_Y_LEN_STEP)
#define P_VPU_PROT3_RPT_LOOP VPU_REG_ADDR(VPU_PROT3_RPT_LOOP)
#define P_VPU_PROT3_RPT_PAT VPU_REG_ADDR(VPU_PROT3_RPT_PAT)
#define P_VPU_PROT3_DDR VPU_REG_ADDR(VPU_PROT3_DDR)
#define P_VPU_PROT3_RBUF_ROOM VPU_REG_ADDR(VPU_PROT3_RBUF_ROOM)
#define P_VPU_PROT3_STAT_0 VPU_REG_ADDR(VPU_PROT3_STAT_0)
#define P_VPU_PROT3_STAT_1 VPU_REG_ADDR(VPU_PROT3_STAT_1)
#define P_VPU_PROT3_STAT_2 VPU_REG_ADDR(VPU_PROT3_STAT_2)
#define P_VPU_PROT3_REQ_ONOFF VPU_REG_ADDR(VPU_PROT3_REQ_ONOFF)
#define P_CSI2_CLK_RESET VPU_REG_ADDR(CSI2_CLK_RESET)
#define P_CSI2_GEN_CTRL0 VPU_REG_ADDR(CSI2_GEN_CTRL0)
#define P_CSI2_FORCE_PIC_SIZE VPU_REG_ADDR(CSI2_FORCE_PIC_SIZE)
#define P_CSI2_DDR_START_ADDR VPU_REG_ADDR(CSI2_DDR_START_ADDR)
#define P_CSI2_DDR_END_ADDR VPU_REG_ADDR(CSI2_DDR_END_ADDR)
#define P_CSI2_INTERRUPT_CTRL_STAT VPU_REG_ADDR(CSI2_INTERRUPT_CTRL_STAT)
#define P_CSI2_PIC_SIZE_STAT VPU_REG_ADDR(CSI2_PIC_SIZE_STAT)
#define P_CSI2_GEN_STAT0 VPU_REG_ADDR(CSI2_GEN_STAT0)
#define P_CSI2_DDR_WRPT_STAT VPU_REG_ADDR(CSI2_DDR_WRPT_STAT)
#define P_CSI2_FS_EMBED_DDR_START VPU_REG_ADDR(CSI2_FS_EMBED_DDR_START)
#define P_CSI2_FS_EMBED_DDR_END VPU_REG_ADDR(CSI2_FS_EMBED_DDR_END)
#define P_CSI2_FE_EMBED_DDR_START VPU_REG_ADDR(CSI2_FE_EMBED_DDR_START)
#define P_CSI2_FE_EMBED_DDR_END VPU_REG_ADDR(CSI2_FE_EMBED_DDR_END)
#define P_CSI2_MEM_PIXEL_BYTE_CNT VPU_REG_ADDR(CSI2_MEM_PIXEL_BYTE_CNT)
#define P_CSI2_MEM_PIXEL_LINE_CNT VPU_REG_ADDR(CSI2_MEM_PIXEL_LINE_CNT)
#define P_CSI2_PIXEL_DDR_START VPU_REG_ADDR(CSI2_PIXEL_DDR_START)
#define P_CSI2_PIXEL_DDR_END VPU_REG_ADDR(CSI2_PIXEL_DDR_END)
#define P_CSI2_USER_DDR_START VPU_REG_ADDR(CSI2_USER_DDR_START)
#define P_CSI2_USER_DDR_END VPU_REG_ADDR(CSI2_USER_DDR_END)
#define P_CSI2_DATA_TYPE_IN_MEM VPU_REG_ADDR(CSI2_DATA_TYPE_IN_MEM)
#define P_CSI2_ERR_STAT0 VPU_REG_ADDR(CSI2_ERR_STAT0)
#define P_CSI2_GEN_CTRL1 VPU_REG_ADDR(CSI2_GEN_CTRL1)
#define P_D2D3_GLB_CTRL VPU_REG_ADDR(D2D3_GLB_CTRL)
#define P_D2D3_DPG_INPIC_SIZE VPU_REG_ADDR(D2D3_DPG_INPIC_SIZE)
#define P_D2D3_DBR_OUTPIC_SIZE VPU_REG_ADDR(D2D3_DBR_OUTPIC_SIZE)
#define P_D2D3_DGEN_WIN_HOR VPU_REG_ADDR(D2D3_DGEN_WIN_HOR)
#define P_D2D3_DGEN_WIN_VER VPU_REG_ADDR(D2D3_DGEN_WIN_VER)
#define P_D2D3_PRE_SCD_H VPU_REG_ADDR(D2D3_PRE_SCD_H)
#define P_D2D3_SCALER_CTRL VPU_REG_ADDR(D2D3_SCALER_CTRL)
#define P_D2D3_CG_THRESHOLD_1 VPU_REG_ADDR(D2D3_CG_THRESHOLD_1)
#define P_D2D3_CG_THRESHOLD_2 VPU_REG_ADDR(D2D3_CG_THRESHOLD_2)
#define P_D2D3_CG_PARAM_1 VPU_REG_ADDR(D2D3_CG_PARAM_1)
#define P_D2D3_CG_PARAM_2 VPU_REG_ADDR(D2D3_CG_PARAM_2)
#define P_D2D3_PRE_SCD_V VPU_REG_ADDR(D2D3_PRE_SCD_V)
#define P_D2D3_D2P_PARAM_1 VPU_REG_ADDR(D2D3_D2P_PARAM_1)
#define P_D2D3_D2P_PARAM_2 VPU_REG_ADDR(D2D3_D2P_PARAM_2)
#define P_D2D3_D2P_PARAM_3 VPU_REG_ADDR(D2D3_D2P_PARAM_3)
#define P_D2D3_SCU18_STEP VPU_REG_ADDR(D2D3_SCU18_STEP)
#define P_D2D3_DPF_LPF_CTRL VPU_REG_ADDR(D2D3_DPF_LPF_CTRL)
#define P_D2D3_DBLD_CG_PARAM VPU_REG_ADDR(D2D3_DBLD_CG_PARAM)
#define P_D2D3_DBLD_MG_PARAM VPU_REG_ADDR(D2D3_DBLD_MG_PARAM)
#define P_D2D3_DBLD_LG_PARAM VPU_REG_ADDR(D2D3_DBLD_LG_PARAM)
#define P_D2D3_DBLD_LPF_HCOEFF VPU_REG_ADDR(D2D3_DBLD_LPF_HCOEFF)
#define P_D2D3_DBLD_LPF_VCOEFF VPU_REG_ADDR(D2D3_DBLD_LPF_VCOEFF)
#define P_D2D3_DBLD_PATH_CTRL VPU_REG_ADDR(D2D3_DBLD_PATH_CTRL)
#define P_D2D3_SCU18_INPIC_SIZE VPU_REG_ADDR(D2D3_SCU18_INPIC_SIZE)
#define P_D2D3_MBDG_CTRL VPU_REG_ADDR(D2D3_MBDG_CTRL)
#define P_D2D3_MBDG_PARAM_0 VPU_REG_ADDR(D2D3_MBDG_PARAM_0)
#define P_D2D3_MBDG_PARAM_1 VPU_REG_ADDR(D2D3_MBDG_PARAM_1)
#define P_D2D3_MBDG_PARAM_2 VPU_REG_ADDR(D2D3_MBDG_PARAM_2)
#define P_D2D3_MBDG_PARAM_3 VPU_REG_ADDR(D2D3_MBDG_PARAM_3)
#define P_D2D3_MBDG_PARAM_4 VPU_REG_ADDR(D2D3_MBDG_PARAM_4)
#define P_D2D3_MBDG_PARAM_5 VPU_REG_ADDR(D2D3_MBDG_PARAM_5)
#define P_D2D3_MBDG_PARAM_6 VPU_REG_ADDR(D2D3_MBDG_PARAM_6)
#define P_D2D3_MBDG_PARAM_7 VPU_REG_ADDR(D2D3_MBDG_PARAM_7)
#define P_D2D3_DBG_CTRL VPU_REG_ADDR(D2D3_DBG_CTRL)
#define P_D2D3_DWMIF_CTRL VPU_REG_ADDR(D2D3_DWMIF_CTRL)
#define P_D2D3_DWMIF_HPOS VPU_REG_ADDR(D2D3_DWMIF_HPOS)
#define P_D2D3_DWMIF_VPOS VPU_REG_ADDR(D2D3_DWMIF_VPOS)
#define P_D2D3_DWMIF_SIZE VPU_REG_ADDR(D2D3_DWMIF_SIZE)
#define P_D2D3_DRMIF_CTRL VPU_REG_ADDR(D2D3_DRMIF_CTRL)
#define P_D2D3_DRMIF_HPOS VPU_REG_ADDR(D2D3_DRMIF_HPOS)
#define P_D2D3_DRMIF_VPOS VPU_REG_ADDR(D2D3_DRMIF_VPOS)
#define P_D2D3_DBR_DDD_CTRL VPU_REG_ADDR(D2D3_DBR_DDD_CTRL)
#define P_D2D3_DBR_DDD_DBG VPU_REG_ADDR(D2D3_DBR_DDD_DBG)
#define P_D2D3_DBR_LRDMX_CTRL VPU_REG_ADDR(D2D3_DBR_LRDMX_CTRL)
#define P_D2D3_CBDG_STATUS_1 VPU_REG_ADDR(D2D3_CBDG_STATUS_1)
#define P_D2D3_MBDG_STATUS_1 VPU_REG_ADDR(D2D3_MBDG_STATUS_1)
#define P_D2D3_MBDG_STATUS_2 VPU_REG_ADDR(D2D3_MBDG_STATUS_2)
#define P_D2D3_MBDG_STATUS_3 VPU_REG_ADDR(D2D3_MBDG_STATUS_3)
#define P_D2D3_MBDG_STATUS_4 VPU_REG_ADDR(D2D3_MBDG_STATUS_4)
#define P_D2D3_MBDG_STATUS_5 VPU_REG_ADDR(D2D3_MBDG_STATUS_5)
#define P_D2D3_MBDG_STATUS_6 VPU_REG_ADDR(D2D3_MBDG_STATUS_6)
#define P_D2D3_MBDG_STATUS_7 VPU_REG_ADDR(D2D3_MBDG_STATUS_7)
#define P_D2D3_DBG_STATUS_1 VPU_REG_ADDR(D2D3_DBG_STATUS_1)
#define P_D2D3_DBG_STATUS_2 VPU_REG_ADDR(D2D3_DBG_STATUS_2)
#define P_D2D3_DRMIF_STATUS VPU_REG_ADDR(D2D3_DRMIF_STATUS)
#define P_D2D3_DWMIF_STATUS VPU_REG_ADDR(D2D3_DWMIF_STATUS)
#define P_D2D3_CBDG_STATUS_2 VPU_REG_ADDR(D2D3_CBDG_STATUS_2)
#define P_D2D3_DBLD_STATUS VPU_REG_ADDR(D2D3_DBLD_STATUS)
#define P_D2D3_RESEV_STATUS1 VPU_REG_ADDR(D2D3_RESEV_STATUS1)
#define P_D2D3_RESEV_STATUS2 VPU_REG_ADDR(D2D3_RESEV_STATUS2)
#define P_MIPI_DSI_DWC_VERSION_OS VPU_REG_ADDR(MIPI_DSI_DWC_VERSION_OS)
#define P_MIPI_DSI_DWC_PWR_UP_OS VPU_REG_ADDR(MIPI_DSI_DWC_PWR_UP_OS)
#define P_MIPI_DSI_DWC_CLKMGR_CFG_OS VPU_REG_ADDR(MIPI_DSI_DWC_CLKMGR_CFG_OS)
#define P_MIPI_DSI_DWC_DPI_VCID_OS VPU_REG_ADDR(MIPI_DSI_DWC_DPI_VCID_OS)
#define P_MIPI_DSI_DWC_DPI_COLOR_CODING_OS VPU_REG_ADDR(MIPI_DSI_DWC_DPI_COLOR_CODING_OS)
#define P_MIPI_DSI_DWC_DPI_CFG_POL_OS VPU_REG_ADDR(MIPI_DSI_DWC_DPI_CFG_POL_OS)
#define P_MIPI_DSI_DWC_DPI_LP_CMD_TIM_OS VPU_REG_ADDR(MIPI_DSI_DWC_DPI_LP_CMD_TIM_OS)
#define P_MIPI_DSI_DWC_PCKHDL_CFG_OS VPU_REG_ADDR(MIPI_DSI_DWC_PCKHDL_CFG_OS)
#define P_MIPI_DSI_DWC_GEN_VCID_OS VPU_REG_ADDR(MIPI_DSI_DWC_GEN_VCID_OS)
#define P_MIPI_DSI_DWC_MODE_CFG_OS VPU_REG_ADDR(MIPI_DSI_DWC_MODE_CFG_OS)
#define P_MIPI_DSI_DWC_VID_MODE_CFG_OS VPU_REG_ADDR(MIPI_DSI_DWC_VID_MODE_CFG_OS)
#define P_MIPI_DSI_DWC_VID_PKT_SIZE_OS VPU_REG_ADDR(MIPI_DSI_DWC_VID_PKT_SIZE_OS)
#define P_MIPI_DSI_DWC_VID_NUM_CHUNKS_OS VPU_REG_ADDR(MIPI_DSI_DWC_VID_NUM_CHUNKS_OS)
#define P_MIPI_DSI_DWC_VID_NULL_SIZE_OS VPU_REG_ADDR(MIPI_DSI_DWC_VID_NULL_SIZE_OS)
#define P_MIPI_DSI_DWC_VID_HSA_TIME_OS VPU_REG_ADDR(MIPI_DSI_DWC_VID_HSA_TIME_OS)
#define P_MIPI_DSI_DWC_VID_HBP_TIME_OS VPU_REG_ADDR(MIPI_DSI_DWC_VID_HBP_TIME_OS)
#define P_MIPI_DSI_DWC_VID_HLINE_TIME_OS VPU_REG_ADDR(MIPI_DSI_DWC_VID_HLINE_TIME_OS)
#define P_MIPI_DSI_DWC_VID_VSA_LINES_OS VPU_REG_ADDR(MIPI_DSI_DWC_VID_VSA_LINES_OS)
#define P_MIPI_DSI_DWC_VID_VBP_LINES_OS VPU_REG_ADDR(MIPI_DSI_DWC_VID_VBP_LINES_OS)
#define P_MIPI_DSI_DWC_VID_VFP_LINES_OS VPU_REG_ADDR(MIPI_DSI_DWC_VID_VFP_LINES_OS)
#define P_MIPI_DSI_DWC_VID_VACTIVE_LINES_OS VPU_REG_ADDR(MIPI_DSI_DWC_VID_VACTIVE_LINES_OS)
#define P_MIPI_DSI_DWC_EDPI_CMD_SIZE_OS VPU_REG_ADDR(MIPI_DSI_DWC_EDPI_CMD_SIZE_OS)
#define P_MIPI_DSI_DWC_CMD_MODE_CFG_OS VPU_REG_ADDR(MIPI_DSI_DWC_CMD_MODE_CFG_OS)
#define P_MIPI_DSI_DWC_GEN_HDR_OS VPU_REG_ADDR(MIPI_DSI_DWC_GEN_HDR_OS)
#define P_MIPI_DSI_DWC_GEN_PLD_DATA_OS VPU_REG_ADDR(MIPI_DSI_DWC_GEN_PLD_DATA_OS)
#define P_MIPI_DSI_DWC_CMD_PKT_STATUS_OS VPU_REG_ADDR(MIPI_DSI_DWC_CMD_PKT_STATUS_OS)
#define P_MIPI_DSI_DWC_TO_CNT_CFG_OS VPU_REG_ADDR(MIPI_DSI_DWC_TO_CNT_CFG_OS)
#define P_MIPI_DSI_DWC_HS_RD_TO_CNT_OS VPU_REG_ADDR(MIPI_DSI_DWC_HS_RD_TO_CNT_OS)
#define P_MIPI_DSI_DWC_LP_RD_TO_CNT_OS VPU_REG_ADDR(MIPI_DSI_DWC_LP_RD_TO_CNT_OS)
#define P_MIPI_DSI_DWC_HS_WR_TO_CNT_OS VPU_REG_ADDR(MIPI_DSI_DWC_HS_WR_TO_CNT_OS)
#define P_MIPI_DSI_DWC_LP_WR_TO_CNT_OS VPU_REG_ADDR(MIPI_DSI_DWC_LP_WR_TO_CNT_OS)
#define P_MIPI_DSI_DWC_BTA_TO_CNT_OS VPU_REG_ADDR(MIPI_DSI_DWC_BTA_TO_CNT_OS)
#define P_MIPI_DSI_DWC_SDF_3D_OS VPU_REG_ADDR(MIPI_DSI_DWC_SDF_3D_OS)
#define P_MIPI_DSI_DWC_LPCLK_CTRL_OS VPU_REG_ADDR(MIPI_DSI_DWC_LPCLK_CTRL_OS)
#define P_MIPI_DSI_DWC_PHY_TMR_LPCLK_CFG_OS VPU_REG_ADDR(MIPI_DSI_DWC_PHY_TMR_LPCLK_CFG_OS)
#define P_MIPI_DSI_DWC_PHY_TMR_CFG_OS VPU_REG_ADDR(MIPI_DSI_DWC_PHY_TMR_CFG_OS)
#define P_MIPI_DSI_DWC_PHY_RSTZ_OS VPU_REG_ADDR(MIPI_DSI_DWC_PHY_RSTZ_OS)
#define P_MIPI_DSI_DWC_PHY_IF_CFG_OS VPU_REG_ADDR(MIPI_DSI_DWC_PHY_IF_CFG_OS)
#define P_MIPI_DSI_DWC_PHY_ULPS_CTRL_OS VPU_REG_ADDR(MIPI_DSI_DWC_PHY_ULPS_CTRL_OS)
#define P_MIPI_DSI_DWC_PHY_TX_TRIGGERS_OS VPU_REG_ADDR(MIPI_DSI_DWC_PHY_TX_TRIGGERS_OS)
#define P_MIPI_DSI_DWC_PHY_STATUS_OS VPU_REG_ADDR(MIPI_DSI_DWC_PHY_STATUS_OS)
#define P_MIPI_DSI_DWC_PHY_TST_CTRL0_OS VPU_REG_ADDR(MIPI_DSI_DWC_PHY_TST_CTRL0_OS)
#define P_MIPI_DSI_DWC_PHY_TST_CTRL1_OS VPU_REG_ADDR(MIPI_DSI_DWC_PHY_TST_CTRL1_OS)
#define P_MIPI_DSI_DWC_INT_ST0_OS VPU_REG_ADDR(MIPI_DSI_DWC_INT_ST0_OS)
#define P_MIPI_DSI_DWC_INT_ST1_OS VPU_REG_ADDR(MIPI_DSI_DWC_INT_ST1_OS)
#define P_MIPI_DSI_DWC_INT_MSK0_OS VPU_REG_ADDR(MIPI_DSI_DWC_INT_MSK0_OS)
#define P_MIPI_DSI_DWC_INT_MSK1_OS VPU_REG_ADDR(MIPI_DSI_DWC_INT_MSK1_OS)
#define P_MIPI_DSI_TOP_SW_RESET VPU_REG_ADDR(MIPI_DSI_TOP_SW_RESET)
#define P_MIPI_DSI_TOP_CLK_CNTL VPU_REG_ADDR(MIPI_DSI_TOP_CLK_CNTL)
#define P_MIPI_DSI_TOP_CNTL VPU_REG_ADDR(MIPI_DSI_TOP_CNTL)
#define P_MIPI_DSI_TOP_SUSPEND_CNTL VPU_REG_ADDR(MIPI_DSI_TOP_SUSPEND_CNTL)
#define P_MIPI_DSI_TOP_SUSPEND_LINE VPU_REG_ADDR(MIPI_DSI_TOP_SUSPEND_LINE)
#define P_MIPI_DSI_TOP_SUSPEND_PIX VPU_REG_ADDR(MIPI_DSI_TOP_SUSPEND_PIX)
#define P_MIPI_DSI_TOP_MEAS_CNTL VPU_REG_ADDR(MIPI_DSI_TOP_MEAS_CNTL)
#define P_MIPI_DSI_TOP_STAT VPU_REG_ADDR(MIPI_DSI_TOP_STAT)
#define P_MIPI_DSI_TOP_MEAS_STAT_TE0 VPU_REG_ADDR(MIPI_DSI_TOP_MEAS_STAT_TE0)
#define P_MIPI_DSI_TOP_MEAS_STAT_TE1 VPU_REG_ADDR(MIPI_DSI_TOP_MEAS_STAT_TE1)
#define P_MIPI_DSI_TOP_MEAS_STAT_VS0 VPU_REG_ADDR(MIPI_DSI_TOP_MEAS_STAT_VS0)
#define P_MIPI_DSI_TOP_MEAS_STAT_VS1 VPU_REG_ADDR(MIPI_DSI_TOP_MEAS_STAT_VS1)
#define P_MIPI_DSI_TOP_INTR_CNTL_STAT VPU_REG_ADDR(MIPI_DSI_TOP_INTR_CNTL_STAT)
#define P_ISP_GAMMA_LUT_ADDR VPU_REG_ADDR(ISP_GAMMA_LUT_ADDR)
#define P_ISP_GAMMA_LUT_DATA VPU_REG_ADDR(ISP_GAMMA_LUT_DATA)
#define P_ISP_DF1024_LUT_ADDR VPU_REG_ADDR(ISP_DF1024_LUT_ADDR)
#define P_ISP_DF1024_LUT_DATA VPU_REG_ADDR(ISP_DF1024_LUT_DATA)
#define P_ISP_LNSD_LUT_ADDR VPU_REG_ADDR(ISP_LNSD_LUT_ADDR)
#define P_ISP_LNSD_LUT_DATA VPU_REG_ADDR(ISP_LNSD_LUT_DATA)
#define P_ISP_HV_SIZE VPU_REG_ADDR(ISP_HV_SIZE)
#define P_ISP_HBLANK VPU_REG_ADDR(ISP_HBLANK)
#define P_ISP_TIMING_MODE VPU_REG_ADDR(ISP_TIMING_MODE)
#define P_ISP_RST_DLY_NUM VPU_REG_ADDR(ISP_RST_DLY_NUM)
#define P_ISP_OUTVS_DLY_NUM VPU_REG_ADDR(ISP_OUTVS_DLY_NUM)
#define P_ISP_DIN_WIND_OFST VPU_REG_ADDR(ISP_DIN_WIND_OFST)
#define P_ISP_FRM_SOFT_RST VPU_REG_ADDR(ISP_FRM_SOFT_RST)
#define P_ISP_RST_SYN_SEL VPU_REG_ADDR(ISP_RST_SYN_SEL)
#define P_ISP_PAT_GEN_CTRL VPU_REG_ADDR(ISP_PAT_GEN_CTRL)
#define P_ISP_PAT_XRAMP_SCAL VPU_REG_ADDR(ISP_PAT_XRAMP_SCAL)
#define P_ISP_PAT_YRAMP_SCAL VPU_REG_ADDR(ISP_PAT_YRAMP_SCAL)
#define P_ISP_PAT_XYIDX_OFST VPU_REG_ADDR(ISP_PAT_XYIDX_OFST)
#define P_ISP_PAT_XYIDX_SCAL VPU_REG_ADDR(ISP_PAT_XYIDX_SCAL)
#define P_ISP_PAT_BAR16_RED0 VPU_REG_ADDR(ISP_PAT_BAR16_RED0)
#define P_ISP_PAT_BAR16_RED1 VPU_REG_ADDR(ISP_PAT_BAR16_RED1)
#define P_ISP_PAT_BAR16_RED2 VPU_REG_ADDR(ISP_PAT_BAR16_RED2)
#define P_ISP_PAT_BAR16_RED3 VPU_REG_ADDR(ISP_PAT_BAR16_RED3)
#define P_ISP_PAT_BAR16_GRN0 VPU_REG_ADDR(ISP_PAT_BAR16_GRN0)
#define P_ISP_PAT_BAR16_GRN1 VPU_REG_ADDR(ISP_PAT_BAR16_GRN1)
#define P_ISP_PAT_BAR16_GRN2 VPU_REG_ADDR(ISP_PAT_BAR16_GRN2)
#define P_ISP_PAT_BAR16_GRN3 VPU_REG_ADDR(ISP_PAT_BAR16_GRN3)
#define P_ISP_PAT_BAR16_BLU0 VPU_REG_ADDR(ISP_PAT_BAR16_BLU0)
#define P_ISP_PAT_BAR16_BLU1 VPU_REG_ADDR(ISP_PAT_BAR16_BLU1)
#define P_ISP_PAT_BAR16_BLU2 VPU_REG_ADDR(ISP_PAT_BAR16_BLU2)
#define P_ISP_PAT_BAR16_BLU3 VPU_REG_ADDR(ISP_PAT_BAR16_BLU3)
#define P_ISP_PAT_DFT_XYIDX VPU_REG_ADDR(ISP_PAT_DFT_XYIDX)
#define P_ISP_PAT_DFT_XYWID VPU_REG_ADDR(ISP_PAT_DFT_XYWID)
#define P_ISP_PAT_DFT_GAIN VPU_REG_ADDR(ISP_PAT_DFT_GAIN)
#define P_ISP_PAT_HVTOTAL VPU_REG_ADDR(ISP_PAT_HVTOTAL)
#define P_ISP_PAT_VDE_SLINE VPU_REG_ADDR(ISP_PAT_VDE_SLINE)
#define P_ISP_OUTHS_PARA VPU_REG_ADDR(ISP_OUTHS_PARA)
#define P_ISP_FRM_DONE_PARA VPU_REG_ADDR(ISP_FRM_DONE_PARA)
#define P_ISP_CLAMPGAIN_CTRL VPU_REG_ADDR(ISP_CLAMPGAIN_CTRL)
#define P_ISP_GAIN_BSCORE_GRBG VPU_REG_ADDR(ISP_GAIN_BSCORE_GRBG)
#define P_ISP_CLAMP_GRBG01 VPU_REG_ADDR(ISP_CLAMP_GRBG01)
#define P_ISP_CLAMP_GRBG23 VPU_REG_ADDR(ISP_CLAMP_GRBG23)
#define P_ISP_GAIN_GRBG01 VPU_REG_ADDR(ISP_GAIN_GRBG01)
#define P_ISP_GAIN_GRBG23 VPU_REG_ADDR(ISP_GAIN_GRBG23)
#define P_ISP_LNS_CTRL VPU_REG_ADDR(ISP_LNS_CTRL)
#define P_ISP_LNS_XYSCAL VPU_REG_ADDR(ISP_LNS_XYSCAL)
#define P_ISP_LNS_XYIDX_SHFT VPU_REG_ADDR(ISP_LNS_XYIDX_SHFT)
#define P_ISP_LNS_SENSOR_GAINGRBG VPU_REG_ADDR(ISP_LNS_SENSOR_GAINGRBG)
#define P_ISP_LNS_POST_OFSTGRBG VPU_REG_ADDR(ISP_LNS_POST_OFSTGRBG)
#define P_ISP_GMR0_CTRL VPU_REG_ADDR(ISP_GMR0_CTRL)
#define P_ISP_DFT_CTRL VPU_REG_ADDR(ISP_DFT_CTRL)
#define P_ISP_DFT_VAR_MINMAX VPU_REG_ADDR(ISP_DFT_VAR_MINMAX)
#define P_ISP_DFT_THDLOW VPU_REG_ADDR(ISP_DFT_THDLOW)
#define P_ISP_DFT_THDHIG VPU_REG_ADDR(ISP_DFT_THDHIG)
#define P_ISP_DFT_CALIBRAT_REF VPU_REG_ADDR(ISP_DFT_CALIBRAT_REF)
#define P_ISP_DFT_CALIBRAT_CTRL VPU_REG_ADDR(ISP_DFT_CALIBRAT_CTRL)
#define P_ISP_DFT_DET0_MANUALTH VPU_REG_ADDR(ISP_DFT_DET0_MANUALTH)
#define P_ISP_DFT_DET1_ADPTLOWTH VPU_REG_ADDR(ISP_DFT_DET1_ADPTLOWTH)
#define P_ISP_DFT_DET1_ADPTHIGTH VPU_REG_ADDR(ISP_DFT_DET1_ADPTHIGTH)
#define P_ISP_DFT_DET1_ADPTNUM0 VPU_REG_ADDR(ISP_DFT_DET1_ADPTNUM0)
#define P_ISP_DFT_DET1_ADPTNUM1 VPU_REG_ADDR(ISP_DFT_DET1_ADPTNUM1)
#define P_ISP_DMS_CTRL0 VPU_REG_ADDR(ISP_DMS_CTRL0)
#define P_ISP_DMS_CTRL1 VPU_REG_ADDR(ISP_DMS_CTRL1)
#define P_ISP_MATRIX_PRE_OFST0_1 VPU_REG_ADDR(ISP_MATRIX_PRE_OFST0_1)
#define P_ISP_MATRIX_PRE_OFST2 VPU_REG_ADDR(ISP_MATRIX_PRE_OFST2)
#define P_ISP_MATRIX_COEF00_01 VPU_REG_ADDR(ISP_MATRIX_COEF00_01)
#define P_ISP_MATRIX_COEF02_10 VPU_REG_ADDR(ISP_MATRIX_COEF02_10)
#define P_ISP_MATRIX_COEF11_12 VPU_REG_ADDR(ISP_MATRIX_COEF11_12)
#define P_ISP_MATRIX_COEF20_21 VPU_REG_ADDR(ISP_MATRIX_COEF20_21)
#define P_ISP_MATRIX_COEF22 VPU_REG_ADDR(ISP_MATRIX_COEF22)
#define P_ISP_MATRIX_POS_OFST0_1 VPU_REG_ADDR(ISP_MATRIX_POS_OFST0_1)
#define P_ISP_MATRIX_POS_OFST2 VPU_REG_ADDR(ISP_MATRIX_POS_OFST2)
#define P_ISP_PKNR_HVBLANK_NUM VPU_REG_ADDR(ISP_PKNR_HVBLANK_NUM)
#define P_ISP_NR_GAUSSIAN_MODE VPU_REG_ADDR(ISP_NR_GAUSSIAN_MODE)
#define P_ISP_PK_HVCON_LPF_MODE VPU_REG_ADDR(ISP_PK_HVCON_LPF_MODE)
#define P_ISP_PK_CON_BLEND_GAIN VPU_REG_ADDR(ISP_PK_CON_BLEND_GAIN)
#define P_ISP_PK_CON_2CIRHPGAIN_TH_RATE VPU_REG_ADDR(ISP_PK_CON_2CIRHPGAIN_TH_RATE)
#define P_ISP_PK_CON_2CIRHPGAIN_LIMIT VPU_REG_ADDR(ISP_PK_CON_2CIRHPGAIN_LIMIT)
#define P_ISP_PK_CON_2CIRBPGAIN_TH_RATE VPU_REG_ADDR(ISP_PK_CON_2CIRBPGAIN_TH_RATE)
#define P_ISP_PK_CON_2CIRBPGAIN_LIMIT VPU_REG_ADDR(ISP_PK_CON_2CIRBPGAIN_LIMIT)
#define P_ISP_PK_CON_2DRTHPGAIN_TH_RATE VPU_REG_ADDR(ISP_PK_CON_2DRTHPGAIN_TH_RATE)
#define P_ISP_PK_CON_2DRTHPGAIN_LIMIT VPU_REG_ADDR(ISP_PK_CON_2DRTHPGAIN_LIMIT)
#define P_ISP_PK_CON_2DRTBPGAIN_TH_RATE VPU_REG_ADDR(ISP_PK_CON_2DRTBPGAIN_TH_RATE)
#define P_ISP_PK_CON_2DRTBPGAIN_LIMIT VPU_REG_ADDR(ISP_PK_CON_2DRTBPGAIN_LIMIT)
#define P_ISP_PK_CIRFB_LPF_MODE VPU_REG_ADDR(ISP_PK_CIRFB_LPF_MODE)
#define P_ISP_PK_DRTFB_LPF_MODE VPU_REG_ADDR(ISP_PK_DRTFB_LPF_MODE)
#define P_ISP_PK_CIRFB_HP_CORING VPU_REG_ADDR(ISP_PK_CIRFB_HP_CORING)
#define P_ISP_PK_CIRFB_BP_CORING VPU_REG_ADDR(ISP_PK_CIRFB_BP_CORING)
#define P_ISP_PK_DRTFB_HP_CORING VPU_REG_ADDR(ISP_PK_DRTFB_HP_CORING)
#define P_ISP_PK_DRTFB_BP_CORING VPU_REG_ADDR(ISP_PK_DRTFB_BP_CORING)
#define P_ISP_PK_CIRFB_BLEND_GAIN VPU_REG_ADDR(ISP_PK_CIRFB_BLEND_GAIN)
#define P_ISP_NR_ALPY_SSD_GAIN_OFST VPU_REG_ADDR(ISP_NR_ALPY_SSD_GAIN_OFST)
#define P_ISP_NR_ALP0Y_ERR2CURV_TH_RATE VPU_REG_ADDR(ISP_NR_ALP0Y_ERR2CURV_TH_RATE)
#define P_ISP_NR_ALP0Y_ERR2CURV_LIMIT VPU_REG_ADDR(ISP_NR_ALP0Y_ERR2CURV_LIMIT)
#define P_ISP_NR_ALP0C_ERR2CURV_TH_RATE VPU_REG_ADDR(ISP_NR_ALP0C_ERR2CURV_TH_RATE)
#define P_ISP_NR_ALP0C_ERR2CURV_LIMIT VPU_REG_ADDR(ISP_NR_ALP0C_ERR2CURV_LIMIT)
#define P_ISP_NR_ALP0_MIN_MAX VPU_REG_ADDR(ISP_NR_ALP0_MIN_MAX)
#define P_ISP_NR_ALP1_MIERR_CORING VPU_REG_ADDR(ISP_NR_ALP1_MIERR_CORING)
#define P_ISP_NR_ALP1_ERR2CURV_TH_RATE VPU_REG_ADDR(ISP_NR_ALP1_ERR2CURV_TH_RATE)
#define P_ISP_NR_ALP1_ERR2CURV_LIMIT VPU_REG_ADDR(ISP_NR_ALP1_ERR2CURV_LIMIT)
#define P_ISP_NR_ALP1_MIN_MAX VPU_REG_ADDR(ISP_NR_ALP1_MIN_MAX)
#define P_ISP_PK_ALP2_MIERR_CORING VPU_REG_ADDR(ISP_PK_ALP2_MIERR_CORING)
#define P_ISP_PK_ALP2_ERR2CURV_TH_RATE VPU_REG_ADDR(ISP_PK_ALP2_ERR2CURV_TH_RATE)
#define P_ISP_PK_ALP2_ERR2CURV_LIMIT VPU_REG_ADDR(ISP_PK_ALP2_ERR2CURV_LIMIT)
#define P_ISP_PK_ALP2_MIN_MAX VPU_REG_ADDR(ISP_PK_ALP2_MIN_MAX)
#define P_ISP_PK_FINALGAIN_HP_BP VPU_REG_ADDR(ISP_PK_FINALGAIN_HP_BP)
#define P_ISP_PK_OS_HORZ_CORE_GAIN VPU_REG_ADDR(ISP_PK_OS_HORZ_CORE_GAIN)
#define P_ISP_PK_OS_VERT_CORE_GAIN VPU_REG_ADDR(ISP_PK_OS_VERT_CORE_GAIN)
#define P_ISP_PK_OS_ADPT_MISC VPU_REG_ADDR(ISP_PK_OS_ADPT_MISC)
#define P_ISP_PK_OS_STATIC VPU_REG_ADDR(ISP_PK_OS_STATIC)
#define P_ISP_PKSDE_MODE_PKGAIN VPU_REG_ADDR(ISP_PKSDE_MODE_PKGAIN)
#define P_ISP_PKSDE_REPLACE_Y_U VPU_REG_ADDR(ISP_PKSDE_REPLACE_Y_U)
#define P_ISP_PKSDE_REPLACE_V VPU_REG_ADDR(ISP_PKSDE_REPLACE_V)
#define P_ISP_PKSDE_BINARY_HIG VPU_REG_ADDR(ISP_PKSDE_BINARY_HIG)
#define P_ISP_PKSDE_BINARY_LOW VPU_REG_ADDR(ISP_PKSDE_BINARY_LOW)
#define P_ISP_PKNR_ENABLE VPU_REG_ADDR(ISP_PKNR_ENABLE)
#define P_ISP_AWB_WIND_LR VPU_REG_ADDR(ISP_AWB_WIND_LR)
#define P_ISP_AWB_WIND_TB VPU_REG_ADDR(ISP_AWB_WIND_TB)
#define P_ISP_AWB_GBGRBR_THRD VPU_REG_ADDR(ISP_AWB_GBGRBR_THRD)
#define P_ISP_AWB_UVTH_YPIECE VPU_REG_ADDR(ISP_AWB_UVTH_YPIECE)
#define P_ISP_AWB_AEC_ENABLE VPU_REG_ADDR(ISP_AWB_AEC_ENABLE)
#define P_ISP_AEC_THRESHOLDS VPU_REG_ADDR(ISP_AEC_THRESHOLDS)
#define P_ISP_AEC_WIND_XYSTART VPU_REG_ADDR(ISP_AEC_WIND_XYSTART)
#define P_ISP_AEC_WIND_XYSTEP VPU_REG_ADDR(ISP_AEC_WIND_XYSTEP)
#define P_ISP_AECRAW_WIND_LR VPU_REG_ADDR(ISP_AECRAW_WIND_LR)
#define P_ISP_AECRAW_WIND_TB VPU_REG_ADDR(ISP_AECRAW_WIND_TB)
#define P_ISP_AFC_FILTER_SEL VPU_REG_ADDR(ISP_AFC_FILTER_SEL)
#define P_ISP_AFC_WIND0_LR VPU_REG_ADDR(ISP_AFC_WIND0_LR)
#define P_ISP_AFC_WIND0_TB VPU_REG_ADDR(ISP_AFC_WIND0_TB)
#define P_ISP_AFC_WIND1_LR VPU_REG_ADDR(ISP_AFC_WIND1_LR)
#define P_ISP_AFC_WIND1_TB VPU_REG_ADDR(ISP_AFC_WIND1_TB)
#define P_ISP_AFC_WIND2_LR VPU_REG_ADDR(ISP_AFC_WIND2_LR)
#define P_ISP_AFC_WIND2_TB VPU_REG_ADDR(ISP_AFC_WIND2_TB)
#define P_ISP_AFC_WIND3_LR VPU_REG_ADDR(ISP_AFC_WIND3_LR)
#define P_ISP_AFC_WIND3_TB VPU_REG_ADDR(ISP_AFC_WIND3_TB)
#define P_ISP_AFC_WIND4_LR VPU_REG_ADDR(ISP_AFC_WIND4_LR)
#define P_ISP_AFC_WIND4_TB VPU_REG_ADDR(ISP_AFC_WIND4_TB)
#define P_ISP_AFC_WIND5_LR VPU_REG_ADDR(ISP_AFC_WIND5_LR)
#define P_ISP_AFC_WIND5_TB VPU_REG_ADDR(ISP_AFC_WIND5_TB)
#define P_ISP_AFC_WIND6_LR VPU_REG_ADDR(ISP_AFC_WIND6_LR)
#define P_ISP_AFC_WIND6_TB VPU_REG_ADDR(ISP_AFC_WIND6_TB)
#define P_ISP_AFC_WIND7_LR VPU_REG_ADDR(ISP_AFC_WIND7_LR)
#define P_ISP_AFC_WIND7_TB VPU_REG_ADDR(ISP_AFC_WIND7_TB)
#define P_ISP_BLNR_CTRL VPU_REG_ADDR(ISP_BLNR_CTRL)
#define P_ISP_BLNR_WIND_LR VPU_REG_ADDR(ISP_BLNR_WIND_LR)
#define P_ISP_BLNR_WIND_TB VPU_REG_ADDR(ISP_BLNR_WIND_TB)
#define P_ISP_RAM_ACC_MODE VPU_REG_ADDR(ISP_RAM_ACC_MODE)
#define P_ISP_DBG_PIXEL_CTRL VPU_REG_ADDR(ISP_DBG_PIXEL_CTRL)
#define P_ISP_DBG_PIXEL_POSITION VPU_REG_ADDR(ISP_DBG_PIXEL_POSITION)
#define P_ISP_RO_DBG_PIXEL_GRBG0_1 VPU_REG_ADDR(ISP_RO_DBG_PIXEL_GRBG0_1)
#define P_ISP_RO_DBG_PIXEL_GRBG2_3 VPU_REG_ADDR(ISP_RO_DBG_PIXEL_GRBG2_3)
#define P_ISP_RO_DFT_LUTMEM_CTRL VPU_REG_ADDR(ISP_RO_DFT_LUTMEM_CTRL)
#define P_ISP_RO_DFT_DET_NUM VPU_REG_ADDR(ISP_RO_DFT_DET_NUM)
#define P_ISP_RO_INFORD_STATE VPU_REG_ADDR(ISP_RO_INFORD_STATE)
#define P_ISP_RO_DINVLD_HVCNT VPU_REG_ADDR(ISP_RO_DINVLD_HVCNT)
#define P_ISP_RO_FRM_HS_STAT VPU_REG_ADDR(ISP_RO_FRM_HS_STAT)
#define P_ISP_RO_ADDR_PORT VPU_REG_ADDR(ISP_RO_ADDR_PORT)
#define P_ISP_RO_DATA_PORT VPU_REG_ADDR(ISP_RO_DATA_PORT)
#define P_ISP_RO_AWB_RED_SUM CBUS_REG_ADDR(ISP_RO_AWB_RED_SUM)
#define P_ISP_RO_AWB_GRN_SUM CBUS_REG_ADDR(ISP_RO_AWB_GRN_SUM)
#define P_ISP_RO_AWB_BLU_SUM CBUS_REG_ADDR(ISP_RO_AWB_BLU_SUM)
#define P_ISP_RO_AWB_RGB_NUM CBUS_REG_ADDR(ISP_RO_AWB_RGB_NUM)
#define P_ISP_RO_AWB_LOW_UNEG_SUM CBUS_REG_ADDR(ISP_RO_AWB_LOW_UNEG_SUM)
#define P_ISP_RO_AWB_LOW_VNEG_SUM CBUS_REG_ADDR(ISP_RO_AWB_LOW_VNEG_SUM)
#define P_ISP_RO_AWB_LOW_UPOS_SUM CBUS_REG_ADDR(ISP_RO_AWB_LOW_UPOS_SUM)
#define P_ISP_RO_AWB_LOW_VPOS_SUM CBUS_REG_ADDR(ISP_RO_AWB_LOW_VPOS_SUM)
#define P_ISP_RO_AWB_LOW_UNEG_NUM CBUS_REG_ADDR(ISP_RO_AWB_LOW_UNEG_NUM)
#define P_ISP_RO_AWB_LOW_VNEG_NUM CBUS_REG_ADDR(ISP_RO_AWB_LOW_VNEG_NUM)
#define P_ISP_RO_AWB_LOW_UPOS_NUM CBUS_REG_ADDR(ISP_RO_AWB_LOW_UPOS_NUM)
#define P_ISP_RO_AWB_LOW_VPOS_NUM CBUS_REG_ADDR(ISP_RO_AWB_LOW_VPOS_NUM)
#define P_ISP_RO_AWB_MID_UNEG_SUM CBUS_REG_ADDR(ISP_RO_AWB_MID_UNEG_SUM)
#define P_ISP_RO_AWB_MID_VNEG_SUM CBUS_REG_ADDR(ISP_RO_AWB_MID_VNEG_SUM)
#define P_ISP_RO_AWB_MID_UPOS_SUM CBUS_REG_ADDR(ISP_RO_AWB_MID_UPOS_SUM)
#define P_ISP_RO_AWB_MID_VPOS_SUM CBUS_REG_ADDR(ISP_RO_AWB_MID_VPOS_SUM)
#define P_ISP_RO_AWB_MID_UNEG_NUM CBUS_REG_ADDR(ISP_RO_AWB_MID_UNEG_NUM)
#define P_ISP_RO_AWB_MID_VNEG_NUM CBUS_REG_ADDR(ISP_RO_AWB_MID_VNEG_NUM)
#define P_ISP_RO_AWB_MID_UPOS_NUM CBUS_REG_ADDR(ISP_RO_AWB_MID_UPOS_NUM)
#define P_ISP_RO_AWB_MID_VPOS_NUM CBUS_REG_ADDR(ISP_RO_AWB_MID_VPOS_NUM)
#define P_ISP_RO_AWB_HIG_UNEG_SUM CBUS_REG_ADDR(ISP_RO_AWB_HIG_UNEG_SUM)
#define P_ISP_RO_AWB_HIG_VNEG_SUM CBUS_REG_ADDR(ISP_RO_AWB_HIG_VNEG_SUM)
#define P_ISP_RO_AWB_HIG_UPOS_SUM CBUS_REG_ADDR(ISP_RO_AWB_HIG_UPOS_SUM)
#define P_ISP_RO_AWB_HIG_VPOS_SUM CBUS_REG_ADDR(ISP_RO_AWB_HIG_VPOS_SUM)
#define P_ISP_RO_AWB_HIG_UNEG_NUM CBUS_REG_ADDR(ISP_RO_AWB_HIG_UNEG_NUM)
#define P_ISP_RO_AWB_HIG_VNEG_NUM CBUS_REG_ADDR(ISP_RO_AWB_HIG_VNEG_NUM)
#define P_ISP_RO_AWB_HIG_UPOS_NUM CBUS_REG_ADDR(ISP_RO_AWB_HIG_UPOS_NUM)
#define P_ISP_RO_AWB_HIG_VPOS_NUM CBUS_REG_ADDR(ISP_RO_AWB_HIG_VPOS_NUM)
#define P_ISP_RO_AEC_LUMA_WIND0_0 CBUS_REG_ADDR(ISP_RO_AEC_LUMA_WIND0_0)
#define P_ISP_RO_AEC_LUMA_WIND0_1 CBUS_REG_ADDR(ISP_RO_AEC_LUMA_WIND0_1)
#define P_ISP_RO_AEC_LUMA_WIND0_2 CBUS_REG_ADDR(ISP_RO_AEC_LUMA_WIND0_2)
#define P_ISP_RO_AEC_LUMA_WIND0_3 CBUS_REG_ADDR(ISP_RO_AEC_LUMA_WIND0_3)
#define P_ISP_RO_AEC_LUMA_WIND1_0 CBUS_REG_ADDR(ISP_RO_AEC_LUMA_WIND1_0)
#define P_ISP_RO_AEC_LUMA_WIND1_1 CBUS_REG_ADDR(ISP_RO_AEC_LUMA_WIND1_1)
#define P_ISP_RO_AEC_LUMA_WIND1_2 CBUS_REG_ADDR(ISP_RO_AEC_LUMA_WIND1_2)
#define P_ISP_RO_AEC_LUMA_WIND1_3 CBUS_REG_ADDR(ISP_RO_AEC_LUMA_WIND1_3)
#define P_ISP_RO_AEC_LUMA_WIND2_0 CBUS_REG_ADDR(ISP_RO_AEC_LUMA_WIND2_0)
#define P_ISP_RO_AEC_LUMA_WIND2_1 CBUS_REG_ADDR(ISP_RO_AEC_LUMA_WIND2_1)
#define P_ISP_RO_AEC_LUMA_WIND2_2 CBUS_REG_ADDR(ISP_RO_AEC_LUMA_WIND2_2)
#define P_ISP_RO_AEC_LUMA_WIND2_3 CBUS_REG_ADDR(ISP_RO_AEC_LUMA_WIND2_3)
#define P_ISP_RO_AEC_LUMA_WIND3_0 CBUS_REG_ADDR(ISP_RO_AEC_LUMA_WIND3_0)
#define P_ISP_RO_AEC_LUMA_WIND3_1 CBUS_REG_ADDR(ISP_RO_AEC_LUMA_WIND3_1)
#define P_ISP_RO_AEC_LUMA_WIND3_2 CBUS_REG_ADDR(ISP_RO_AEC_LUMA_WIND3_2)
#define P_ISP_RO_AEC_LUMA_WIND3_3 CBUS_REG_ADDR(ISP_RO_AEC_LUMA_WIND3_3)
#define P_ISP_RO_AECRAW_NUM_RED CBUS_REG_ADDR(ISP_RO_AECRAW_NUM_RED)
#define P_ISP_RO_AECRAW_NUM_GREEN CBUS_REG_ADDR(ISP_RO_AECRAW_NUM_GREEN)
#define P_ISP_RO_AECRAW_NUM_BLUE CBUS_REG_ADDR(ISP_RO_AECRAW_NUM_BLUE)
#define P_ISP_RO_AFC_WIND0_F0 CBUS_REG_ADDR(ISP_RO_AFC_WIND0_F0)
#define P_ISP_RO_AFC_WIND0_F1 CBUS_REG_ADDR(ISP_RO_AFC_WIND0_F1)
#define P_ISP_RO_AFC_WIND1_F0 CBUS_REG_ADDR(ISP_RO_AFC_WIND1_F0)
#define P_ISP_RO_AFC_WIND1_F1 CBUS_REG_ADDR(ISP_RO_AFC_WIND1_F1)
#define P_ISP_RO_AFC_WIND2_F0 CBUS_REG_ADDR(ISP_RO_AFC_WIND2_F0)
#define P_ISP_RO_AFC_WIND2_F1 CBUS_REG_ADDR(ISP_RO_AFC_WIND2_F1)
#define P_ISP_RO_AFC_WIND3_F0 CBUS_REG_ADDR(ISP_RO_AFC_WIND3_F0)
#define P_ISP_RO_AFC_WIND3_F1 CBUS_REG_ADDR(ISP_RO_AFC_WIND3_F1)
#define P_ISP_RO_AFC_WIND4_F0 CBUS_REG_ADDR(ISP_RO_AFC_WIND4_F0)
#define P_ISP_RO_AFC_WIND4_F1 CBUS_REG_ADDR(ISP_RO_AFC_WIND4_F1)
#define P_ISP_RO_AFC_WIND5_F0 CBUS_REG_ADDR(ISP_RO_AFC_WIND5_F0)
#define P_ISP_RO_AFC_WIND5_F1 CBUS_REG_ADDR(ISP_RO_AFC_WIND5_F1)
#define P_ISP_RO_AFC_WIND6_F0 CBUS_REG_ADDR(ISP_RO_AFC_WIND6_F0)
#define P_ISP_RO_AFC_WIND6_F1 CBUS_REG_ADDR(ISP_RO_AFC_WIND6_F1)
#define P_ISP_RO_AFC_WIND7_F0 CBUS_REG_ADDR(ISP_RO_AFC_WIND7_F0)
#define P_ISP_RO_AFC_WIND7_F1 CBUS_REG_ADDR(ISP_RO_AFC_WIND7_F1)
#define P_ISP_RO_BLNR_GRBG_DCSUM0 CBUS_REG_ADDR(ISP_RO_BLNR_GRBG_DCSUM0)
#define P_ISP_RO_BLNR_GRBG_DCSUM1 CBUS_REG_ADDR(ISP_RO_BLNR_GRBG_DCSUM1)
#define P_ISP_RO_BLNR_GRBG_DCSUM2 CBUS_REG_ADDR(ISP_RO_BLNR_GRBG_DCSUM2)
#define P_ISP_RO_BLNR_GRBG_DCSUM3 CBUS_REG_ADDR(ISP_RO_BLNR_GRBG_DCSUM3)
#define P_ISP_RO_BLNR_GRBG_ACSUM0 CBUS_REG_ADDR(ISP_RO_BLNR_GRBG_ACSUM0)
#define P_ISP_RO_BLNR_GRBG_ACSUM1 CBUS_REG_ADDR(ISP_RO_BLNR_GRBG_ACSUM1)
#define P_ISP_RO_BLNR_GRBG_ACSUM2 CBUS_REG_ADDR(ISP_RO_BLNR_GRBG_ACSUM2)
#define P_ISP_RO_BLNR_GRBG_ACSUM3 CBUS_REG_ADDR(ISP_RO_BLNR_GRBG_ACSUM3)
#define P_BT_CTRL CBUS_REG_ADDR(BT_CTRL)
#define P_BT_VBISTART CBUS_REG_ADDR(BT_VBISTART)
#define P_BT_VBIEND CBUS_REG_ADDR(BT_VBIEND)
#define P_BT_FIELDSADR CBUS_REG_ADDR(BT_FIELDSADR)
#define P_BT_LINECTRL CBUS_REG_ADDR(BT_LINECTRL)
#define P_BT_VIDEOSTART CBUS_REG_ADDR(BT_VIDEOSTART)
#define P_BT_VIDEOEND CBUS_REG_ADDR(BT_VIDEOEND)
#define P_BT_SLICELINE0 CBUS_REG_ADDR(BT_SLICELINE0)
#define P_BT_SLICELINE1 CBUS_REG_ADDR(BT_SLICELINE1)
#define P_BT_PORT_CTRL CBUS_REG_ADDR(BT_PORT_CTRL)
#define P_BT_SWAP_CTRL CBUS_REG_ADDR(BT_SWAP_CTRL)
#define P_BT_ANCISADR CBUS_REG_ADDR(BT_ANCISADR)
#define P_BT_ANCIEADR CBUS_REG_ADDR(BT_ANCIEADR)
#define P_BT_AFIFO_CTRL CBUS_REG_ADDR(BT_AFIFO_CTRL)
#define P_BT_601_CTRL0 CBUS_REG_ADDR(BT_601_CTRL0)
#define P_BT_601_CTRL1 CBUS_REG_ADDR(BT_601_CTRL1)
#define P_BT_601_CTRL2 CBUS_REG_ADDR(BT_601_CTRL2)
#define P_BT_601_CTRL3 CBUS_REG_ADDR(BT_601_CTRL3)
#define P_BT_FIELD_LUMA CBUS_REG_ADDR(BT_FIELD_LUMA)
#define P_BT_RAW_CTRL CBUS_REG_ADDR(BT_RAW_CTRL)
#define P_BT_STATUS CBUS_REG_ADDR(BT_STATUS)
#define P_BT_INT_CTRL CBUS_REG_ADDR(BT_INT_CTRL)
#define P_BT_ANCI_STATUS CBUS_REG_ADDR(BT_ANCI_STATUS)
#define P_BT_VLINE_STATUS CBUS_REG_ADDR(BT_VLINE_STATUS)
#define P_BT_AFIFO_PTR CBUS_REG_ADDR(BT_AFIFO_PTR)
#define P_BT_JPEGBYTENUM CBUS_REG_ADDR(BT_JPEGBYTENUM)
#define P_BT_ERR_CNT CBUS_REG_ADDR(BT_ERR_CNT)
#define P_BT_JPEG_STATUS0 CBUS_REG_ADDR(BT_JPEG_STATUS0)
#define P_BT_JPEG_STATUS1 CBUS_REG_ADDR(BT_JPEG_STATUS1)
#define P_BT_LCNT_STATUS CBUS_REG_ADDR(BT_LCNT_STATUS)
#define P_BT_PCNT_STATUS CBUS_REG_ADDR(BT_PCNT_STATUS)
#define P_BT656_ADDR_END CBUS_REG_ADDR(BT656_ADDR_END)
/**
APB Bus registers
**/
#define P_PCTL_SCFG_ADDR APB_REG_ADDR(PCTL_SCFG_ADDR)
#define P_PCTL_SCTL_ADDR APB_REG_ADDR(PCTL_SCTL_ADDR)
#define P_PCTL_STAT_ADDR APB_REG_ADDR(PCTL_STAT_ADDR)
#define P_PCTL_MCMD_ADDR APB_REG_ADDR(PCTL_MCMD_ADDR)
#define P_PCTL_POWCTL_ADDR APB_REG_ADDR(PCTL_POWCTL_ADDR)
#define P_PCTL_POWSTAT_ADDR APB_REG_ADDR(PCTL_POWSTAT_ADDR)
#define P_PCTL_MCFG_ADDR APB_REG_ADDR(PCTL_MCFG_ADDR)
#define P_PCTL_PPCFG_ADDR APB_REG_ADDR(PCTL_PPCFG_ADDR)
#define P_PCTL_MSTAT_ADDR APB_REG_ADDR(PCTL_MSTAT_ADDR)
#define P_PCTL_ODTCFG_ADDR APB_REG_ADDR(PCTL_ODTCFG_ADDR)
#define P_PCTL_DQSECFG_ADDR APB_REG_ADDR(PCTL_DQSECFG_ADDR)
#define P_PCTL_DTUPDES_ADDR APB_REG_ADDR(PCTL_DTUPDES_ADDR)
#define P_PCTL_DTUNA_ADDR APB_REG_ADDR(PCTL_DTUNA_ADDR)
#define P_PCTL_DTUNE_ADDR APB_REG_ADDR(PCTL_DTUNE_ADDR)
#define P_PCTL_DTUPRD0_ADDR APB_REG_ADDR(PCTL_DTUPRD0_ADDR)
#define P_PCTL_DTUPRD1_ADDR APB_REG_ADDR(PCTL_DTUPRD1_ADDR)
#define P_PCTL_DTUPRD2_ADDR APB_REG_ADDR(PCTL_DTUPRD2_ADDR)
#define P_PCTL_DTUPRD3_ADDR APB_REG_ADDR(PCTL_DTUPRD3_ADDR)
#define P_PCTL_DTUAWDT_ADDR APB_REG_ADDR(PCTL_DTUAWDT_ADDR)
#define P_PCTL_TOGCNT1U_ADDR APB_REG_ADDR(PCTL_TOGCNT1U_ADDR)
#define P_PCTL_TINIT_ADDR APB_REG_ADDR(PCTL_TINIT_ADDR)
#define P_PCTL_TRSTH_ADDR APB_REG_ADDR(PCTL_TRSTH_ADDR)
#define P_PCTL_TOGCNT100N_ADDR APB_REG_ADDR(PCTL_TOGCNT100N_ADDR)
#define P_PCTL_TREFI_ADDR APB_REG_ADDR(PCTL_TREFI_ADDR)
#define P_PCTL_TMRD_ADDR APB_REG_ADDR(PCTL_TMRD_ADDR)
#define P_PCTL_TRFC_ADDR APB_REG_ADDR(PCTL_TRFC_ADDR)
#define P_PCTL_TRP_ADDR APB_REG_ADDR(PCTL_TRP_ADDR)
#define P_PCTL_TRTW_ADDR APB_REG_ADDR(PCTL_TRTW_ADDR)
#define P_PCTL_TAL_ADDR APB_REG_ADDR(PCTL_TAL_ADDR)
#define P_PCTL_TCL_ADDR APB_REG_ADDR(PCTL_TCL_ADDR)
#define P_PCTL_TCWL_ADDR APB_REG_ADDR(PCTL_TCWL_ADDR)
#define P_PCTL_TRAS_ADDR APB_REG_ADDR(PCTL_TRAS_ADDR)
#define P_PCTL_TRC_ADDR APB_REG_ADDR(PCTL_TRC_ADDR)
#define P_PCTL_TRCD_ADDR APB_REG_ADDR(PCTL_TRCD_ADDR)
#define P_PCTL_TRRD_ADDR APB_REG_ADDR(PCTL_TRRD_ADDR)
#define P_PCTL_TRTP_ADDR APB_REG_ADDR(PCTL_TRTP_ADDR)
#define P_PCTL_TWR_ADDR APB_REG_ADDR(PCTL_TWR_ADDR)
#define P_PCTL_TWTR_ADDR APB_REG_ADDR(PCTL_TWTR_ADDR)
#define P_PCTL_TEXSR_ADDR APB_REG_ADDR(PCTL_TEXSR_ADDR)
#define P_PCTL_TXP_ADDR APB_REG_ADDR(PCTL_TXP_ADDR)
#define P_PCTL_TXPDLL_ADDR APB_REG_ADDR(PCTL_TXPDLL_ADDR)
#define P_PCTL_TZQCS_ADDR APB_REG_ADDR(PCTL_TZQCS_ADDR)
#define P_PCTL_TZQCSI_ADDR APB_REG_ADDR(PCTL_TZQCSI_ADDR)
#define P_PCTL_TDQS_ADDR APB_REG_ADDR(PCTL_TDQS_ADDR)
#define P_PCTL_TCKSRE_ADDR APB_REG_ADDR(PCTL_TCKSRE_ADDR)
#define P_PCTL_TCKSRX_ADDR APB_REG_ADDR(PCTL_TCKSRX_ADDR)
#define P_PCTL_TCKE_ADDR APB_REG_ADDR(PCTL_TCKE_ADDR)
#define P_PCTL_TMOD_ADDR APB_REG_ADDR(PCTL_TMOD_ADDR)
#define P_PCTL_TRSTL_ADDR APB_REG_ADDR(PCTL_TRSTL_ADDR)
#define P_PCTL_TZQCL_ADDR APB_REG_ADDR(PCTL_TZQCL_ADDR)
#define P_PCTL_DWLCFG0_ADDR APB_REG_ADDR(PCTL_DWLCFG0_ADDR)
#define P_PCTL_DWLCFG1_ADDR APB_REG_ADDR(PCTL_DWLCFG1_ADDR)
#define P_PCTL_DWLCFG2_ADDR APB_REG_ADDR(PCTL_DWLCFG2_ADDR)
#define P_PCTL_DWLCFG3_ADDR APB_REG_ADDR(PCTL_DWLCFG3_ADDR)
#define P_PCTL_ECCCFG_ADDR APB_REG_ADDR(PCTL_ECCCFG_ADDR)
#define P_PCTL_ECCTST_ADDR APB_REG_ADDR(PCTL_ECCTST_ADDR)
#define P_PCTL_ECCCLR_ADDR APB_REG_ADDR(PCTL_ECCCLR_ADDR)
#define P_PCTL_ECCLOG_ADDR APB_REG_ADDR(PCTL_ECCLOG_ADDR)
#define P_PCTL_ADDRMAP_ADDR APB_REG_ADDR(PCTL_ADDRMAP_ADDR)
#define P_PCTL_IDDEC0_ADDR APB_REG_ADDR(PCTL_IDDEC0_ADDR)
#define P_PCTL_IDDEC1_ADDR APB_REG_ADDR(PCTL_IDDEC1_ADDR)
#define P_PCTL_DTUWACTL_ADDR APB_REG_ADDR(PCTL_DTUWACTL_ADDR)
#define P_PCTL_DTURACTL_ADDR APB_REG_ADDR(PCTL_DTURACTL_ADDR)
#define P_PCTL_DTUCFG_ADDR APB_REG_ADDR(PCTL_DTUCFG_ADDR)
#define P_PCTL_DTUECTL_ADDR APB_REG_ADDR(PCTL_DTUECTL_ADDR)
#define P_PCTL_DTUWD0_ADDR APB_REG_ADDR(PCTL_DTUWD0_ADDR)
#define P_PCTL_DTUWD1_ADDR APB_REG_ADDR(PCTL_DTUWD1_ADDR)
#define P_PCTL_DTUWD2_ADDR APB_REG_ADDR(PCTL_DTUWD2_ADDR)
#define P_PCTL_DTUWD3_ADDR APB_REG_ADDR(PCTL_DTUWD3_ADDR)
#define P_PCTL_DTUWDM_ADDR APB_REG_ADDR(PCTL_DTUWDM_ADDR)
#define P_PCTL_DTURD0_ADDR APB_REG_ADDR(PCTL_DTURD0_ADDR)
#define P_PCTL_DTURD1_ADDR APB_REG_ADDR(PCTL_DTURD1_ADDR)
#define P_PCTL_DTURD2_ADDR APB_REG_ADDR(PCTL_DTURD2_ADDR)
#define P_PCTL_DTURD3_ADDR APB_REG_ADDR(PCTL_DTURD3_ADDR)
#define P_PCTL_DTULFSRWD_ADDR APB_REG_ADDR(PCTL_DTULFSRWD_ADDR)
#define P_PCTL_DTULFSRRD_ADDR APB_REG_ADDR(PCTL_DTULFSRRD_ADDR)
#define P_PCTL_DTUEAF_ADDR APB_REG_ADDR(PCTL_DTUEAF_ADDR)
#define P_PCTL_PHYCR_ADDR APB_REG_ADDR(PCTL_PHYCR_ADDR)
#define P_PCTL_PHYSR_ADDR APB_REG_ADDR(PCTL_PHYSR_ADDR)
#define P_PCTL_IOCR_ADDR APB_REG_ADDR(PCTL_IOCR_ADDR)
#define P_PCTL_RSLR0_ADDR APB_REG_ADDR(PCTL_RSLR0_ADDR)
#define P_PCTL_RSLR1_ADDR APB_REG_ADDR(PCTL_RSLR1_ADDR)
#define P_PCTL_RSLR2_ADDR APB_REG_ADDR(PCTL_RSLR2_ADDR)
#define P_PCTL_RSLR3_ADDR APB_REG_ADDR(PCTL_RSLR3_ADDR)
#define P_PCTL_RDGR0_ADDR APB_REG_ADDR(PCTL_RDGR0_ADDR)
#define P_PCTL_RDGR1_ADDR APB_REG_ADDR(PCTL_RDGR1_ADDR)
#define P_PCTL_RDGR2_ADDR APB_REG_ADDR(PCTL_RDGR2_ADDR)
#define P_PCTL_RDGR3_ADDR APB_REG_ADDR(PCTL_RDGR3_ADDR)
#define P_PCTL_ZQCR_ADDR APB_REG_ADDR(PCTL_ZQCR_ADDR)
#define P_PCTL_ZQSR_ADDR APB_REG_ADDR(PCTL_ZQSR_ADDR)
#define P_PCTL_DLLCR_ADDR APB_REG_ADDR(PCTL_DLLCR_ADDR)
#define P_PCTL_DLLCR0_ADDR APB_REG_ADDR(PCTL_DLLCR0_ADDR)
#define P_PCTL_DLLCR1_ADDR APB_REG_ADDR(PCTL_DLLCR1_ADDR)
#define P_PCTL_DLLCR2_ADDR APB_REG_ADDR(PCTL_DLLCR2_ADDR)
#define P_PCTL_DLLCR3_ADDR APB_REG_ADDR(PCTL_DLLCR3_ADDR)
#define P_PCTL_DLLCR4_ADDR APB_REG_ADDR(PCTL_DLLCR4_ADDR)
#define P_PCTL_DLLCR5_ADDR APB_REG_ADDR(PCTL_DLLCR5_ADDR)
#define P_PCTL_DLLCR6_ADDR APB_REG_ADDR(PCTL_DLLCR6_ADDR)
#define P_PCTL_DLLCR7_ADDR APB_REG_ADDR(PCTL_DLLCR7_ADDR)
#define P_PCTL_DLLCR8_ADDR APB_REG_ADDR(PCTL_DLLCR8_ADDR)
#define P_PCTL_DLLCR9_ADDR APB_REG_ADDR(PCTL_DLLCR9_ADDR)
#define P_PCTL_DQTR0_ADDR APB_REG_ADDR(PCTL_DQTR0_ADDR)
#define P_PCTL_DQTR1_ADDR APB_REG_ADDR(PCTL_DQTR1_ADDR)
#define P_PCTL_DQTR2_ADDR APB_REG_ADDR(PCTL_DQTR2_ADDR)
#define P_PCTL_DQTR3_ADDR APB_REG_ADDR(PCTL_DQTR3_ADDR)
#define P_PCTL_DQTR4_ADDR APB_REG_ADDR(PCTL_DQTR4_ADDR)
#define P_PCTL_DQTR5_ADDR APB_REG_ADDR(PCTL_DQTR5_ADDR)
#define P_PCTL_DQTR6_ADDR APB_REG_ADDR(PCTL_DQTR6_ADDR)
#define P_PCTL_DQTR7_ADDR APB_REG_ADDR(PCTL_DQTR7_ADDR)
#define P_PCTL_DQTR8_ADDR APB_REG_ADDR(PCTL_DQTR8_ADDR)
#define P_PCTL_DQSTR_ADDR APB_REG_ADDR(PCTL_DQSTR_ADDR)
#define P_PCTL_DQSNTR_ADDR APB_REG_ADDR(PCTL_DQSNTR_ADDR)
#define P_PCTL_PHYPVTCFG_ADDR APB_REG_ADDR(PCTL_PHYPVTCFG_ADDR)
#define P_PCTL_PHYPVTSTAT_ADDR APB_REG_ADDR(PCTL_PHYPVTSTAT_ADDR)
#define P_PCTL_PHYTUPDON_ADDR APB_REG_ADDR(PCTL_PHYTUPDON_ADDR)
#define P_PCTL_PHYTUPDDLY_ADDR APB_REG_ADDR(PCTL_PHYTUPDDLY_ADDR)
#define P_PCTL_PVTTUPDON_ADDR APB_REG_ADDR(PCTL_PVTTUPDON_ADDR)
#define P_PCTL_PVTTUPDDLY_ADDR APB_REG_ADDR(PCTL_PVTTUPDDLY_ADDR)
#define P_PCTL_PHYPVTUPDI_ADDR APB_REG_ADDR(PCTL_PHYPVTUPDI_ADDR)
#define P_PCTL_SCHCFG_ADDR APB_REG_ADDR(PCTL_SCHCFG_ADDR)
#define P_PCTL_IPVR_ADDR APB_REG_ADDR(PCTL_IPVR_ADDR)
#define P_PCTL_IPTR_ADDR APB_REG_ADDR(PCTL_IPTR_ADDR)

#define P_EFUSE_CNTL0		(0xDA000000)
#define P_EFUSE_CNTL1		(0xDA000004)
#define P_EFUSE_CNTL2		(0xDA000008)
#define P_EFUSE_CNTL3		(0xDA00000C)
#define P_EFUSE_CNTL4		(0xDA000010)


// ---------------------------
// RTC (4)
// ---------------------------
//#define P_AO_RTC_ADDR0               (0xc8100000 | (0x01 << 10) | (0xd0 << 2))
//#define P_AO_RTC_ADDR1               (0xc8100000 | (0x01 << 10) | (0xd1 << 2))
//#define P_AO_RTC_ADDR2               (0xc8100000 | (0x01 << 10) | (0xd2 << 2))
//#define P_AO_RTC_ADDR3               (0xc8100000 | (0x01 << 10) | (0xd3 << 2))
//#define P_AO_RTC_ADDR4               (0xc8100000 | (0x01 << 10) | (0xd4 << 2))
#define P_SYS_CPU_0_IRQ_IN0_INTR_MASK CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN0_INTR_MASK)
#define P_SYS_CPU_0_IRQ_IN0_INTR_STAT CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN0_INTR_STAT)


#define SECBUS2_REG_ADDR(reg)       (0xda004000+((reg)<<2))

#define AO_SECURE_REG0 0x00 	///../ucode/secure_apb.h:19
#define P_AO_SECURE_REG0 		SECBUS2_REG_ADDR(AO_SECURE_REG0)
#define AO_SECURE_REG1 0x01 	///../ucode/secure_apb.h:20
#define P_AO_SECURE_REG1 		SECBUS2_REG_ADDR(AO_SECURE_REG1)
#define AO_SECURE_REG2 0x02 	///../ucode/secure_apb.h:21
#define P_AO_SECURE_REG2 		SECBUS2_REG_ADDR(AO_SECURE_REG2)
#define SEC_BLKMV_AES_REG0 0x00 	///../ucode/secure_apb.h:34
#define P_SEC_BLKMV_AES_REG0 		SECBUS2_REG_ADDR(SEC_BLKMV_AES_REG0)
#define SEC_BLKMV_AES_W0 0x01 	///../ucode/secure_apb.h:35
#define P_SEC_BLKMV_AES_W0 		SECBUS2_REG_ADDR(SEC_BLKMV_AES_W0)
#define SEC_BLKMV_AES_W1 0x02 	///../ucode/secure_apb.h:36
#define P_SEC_BLKMV_AES_W1 		SECBUS2_REG_ADDR(SEC_BLKMV_AES_W1)
#define SEC_BLKMV_AES_W2 0x03 	///../ucode/secure_apb.h:37
#define P_SEC_BLKMV_AES_W2 		SECBUS2_REG_ADDR(SEC_BLKMV_AES_W2)
#define SEC_BLKMV_AES_W3 0x04 	///../ucode/secure_apb.h:38
#define P_SEC_BLKMV_AES_W3 		SECBUS2_REG_ADDR(SEC_BLKMV_AES_W3)
#define SEC_BLKMV_AES_R0 0x05 	///../ucode/secure_apb.h:39
#define P_SEC_BLKMV_AES_R0 		SECBUS2_REG_ADDR(SEC_BLKMV_AES_R0)
#define SEC_BLKMV_AES_R1 0x06 	///../ucode/secure_apb.h:40
#define P_SEC_BLKMV_AES_R1 		SECBUS2_REG_ADDR(SEC_BLKMV_AES_R1)
#define SEC_BLKMV_AES_R2 0x07 	///../ucode/secure_apb.h:41
#define P_SEC_BLKMV_AES_R2 		SECBUS2_REG_ADDR(SEC_BLKMV_AES_R2)
#define SEC_BLKMV_AES_R3 0x08 	///../ucode/secure_apb.h:42
#define P_SEC_BLKMV_AES_R3 		SECBUS2_REG_ADDR(SEC_BLKMV_AES_R3)
#define SEC_BLKMV_TDES_LAST_IV_LO 0x09 	///../ucode/secure_apb.h:43
#define P_SEC_BLKMV_TDES_LAST_IV_LO 		SECBUS2_REG_ADDR(SEC_BLKMV_TDES_LAST_IV_LO)
#define SEC_BLKMV_TDES_LAST_IV_HI 0x0a 	///../ucode/secure_apb.h:44
#define P_SEC_BLKMV_TDES_LAST_IV_HI 		SECBUS2_REG_ADDR(SEC_BLKMV_TDES_LAST_IV_HI)
#define SEC_BLKMV_AES_IV_0 0x0b 	///../ucode/secure_apb.h:45
#define P_SEC_BLKMV_AES_IV_0 		SECBUS2_REG_ADDR(SEC_BLKMV_AES_IV_0)
#define SEC_BLKMV_AES_IV_1 0x0c 	///../ucode/secure_apb.h:46
#define P_SEC_BLKMV_AES_IV_1 		SECBUS2_REG_ADDR(SEC_BLKMV_AES_IV_1)
#define SEC_BLKMV_AES_IV_2 0x0d 	///../ucode/secure_apb.h:47
#define P_SEC_BLKMV_AES_IV_2 		SECBUS2_REG_ADDR(SEC_BLKMV_AES_IV_2)
#define SEC_BLKMV_AES_IV_3 0x0e 	///../ucode/secure_apb.h:48
#define P_SEC_BLKMV_AES_IV_3 		SECBUS2_REG_ADDR(SEC_BLKMV_AES_IV_3)
#define HDMI_ADDR_PORT 0x2000
#define P_HDMI_ADDR_PORT            APB_HDMI_REG_ADDR(HDMI_ADDR_PORT)
#define HDMI_DATA_PORT 0x2004
#define P_HDMI_DATA_PORT            APB_HDMI_REG_ADDR(HDMI_DATA_PORT)
#define HDMI_CTRL_PORT 0x2008
#define P_HDMI_CTRL_PORT            APB_HDMI_REG_ADDR(HDMI_CTRL_PORT)
#endif
